Introduction

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Table 2. EMAC1_EN Pin Description (continued)

Value Description

1EMAC1 is enabled and used.

Pulls on EMAC1 I/O are disabled (except RGMII pins) and the corresponding I/O buffers are powered up except RGMII output-only pins.

NOTE: RGMII buffers are HSTL buffers with no internal pulls. RGMII output only pins will always be powered down even when the module is enabled.

EMAC1_EN is also software programmable through the DEVCTL register. A write to the DEVCTL register is key-protected by the DEVCTL_KEY register. For details of MACSEL0, MACSEL1, and EMAC1_EN decoding, see Section 2.3.

1.4Industry Standard(s) Compliance Statement

The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. ISO/IEC has also adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-3:2000(E).

In difference from this standard, the EMAC peripheral integrated with the TCI6486/C6472 device does not use the transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC intentionally generates an incorrect check sum by inverting the frame CRC so that the network detects the transmitted frame as an error.

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C6472/TCI6486 EMAC/MDIO

SPRUEF8F –March 2006 –Revised November 2010

 

 

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Texas Instruments TMS320TCI6486 manual Industry Standards Compliance Statement