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Texas Instruments TMS320TCI6486 manual MAC Interrupt Mask Clear Register Macintmaskclear

Models: TMS320TCI6486

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5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 62 and described in Table 56.

Figure 62. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

31			16
	Reserved

	R-0
15	2	1	0

Reserved		HOST	STAT
Reserved		MASK	MASK
		MASK	MASK

R-0		R/WC-0	R/WC-0

LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n= value after reset

Table 56. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	Reserved

1	HOSTMASK		Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

0	STATMASK		Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

114	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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Texas Instruments TMS320TCI6486 manual MAC Interrupt Mask Clear Register Macintmaskclear

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramEMAC1EN Pin Description Serial Management Interface PinsSignal Description Value DescriptionIndustry Standards Compliance Statement MII Clocking Emac Clock SpecificationsClock Control Rmii ClockingRgmii Clocking Memory MapGmii Clocking 5 S3MII ClockingSystem-Level Connections EMAC0 Interface Selection PinsEMAC1 Interface Selection Pins MACSEL020, MACSEL110, and EMAC1EN DecodingMedia Independent Interface MII Connections S3MII Rgmii RmiiEmac and Mdio Signals for MII Interface Signal Name DescriptionRmtxen Emac and Mdio Signals for Rmii InterfaceReduced Media Independent Interface Rmii Connections RmcrsdvGigabit Media Independent Interface Gmii Connections RmrxerEmac and Mdio Signals for Gmii Interface GmtclkRgtxctl Emac and Mdio Signals for Rgmii InterfaceRgtxc RgrefclkRgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes DescriptionMultiple Access Protocol Programming Interface Packet Buffer DescriptorsBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor QueuesTransmit and Receive Emac Interrupts SOP EOP Owner EOQ Tdown Pass Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format Cmplt CRCBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd-of-Queue EOQ Flag End-of-Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure FormatNext Descriptor Pointer Fragment Flag Jabber FlagOversize Flag Undersized FlagCommunications Port Programming Interface Cppi Ethernet Multicore Interrupt Combiner Emic ModuleEmic Block Diagram Pacing Block EvtoutTimed Delay State Machine Tdsm Tdsm State Transition DiagramDSM State Transition Diagram Divide-by-N State Machine DSMTransmit Pacer and Interrupt Combiner Tpic Transmit Pacer and Interrupt CombinerReceive Pacer and Interrupt Combiner Rpic Receive Pacer and Interrupt CombinerManagement Data Input/Output Mdio Module Common Interrupt Combiner CICMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio ModuleExample of Mdio Register Access Code Writing Data to a PHY RegisterReading Data From a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadrEmac Module Emac Module ComponentsEmac Module Operational Overview Receive Control Media Independent InterfacesData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow ControlCRC Insertion Data TransmissionTransmit Control Adaptive Performance Optimization APOBack Off Transmit Flow ControlSpeed, Duplex, and Pause Frame Support Receive DMA Host ConfigurationPacket Receive Operation Receive Channel EnablingHardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Receive Frame ClassificationReceive Frame Treatment Summary Promiscuous Receive ModeRxmbpenable Bits Frame TreatmentReceive Overrun Transmit DMA Host ConfigurationPacket Transmit Operation Middle-of-Frame Overrun TreatmentReceive and Transmit Latency Transfer Node PriorityTransmit Channel Teardown Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Rgmii TransmissionEmic Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Mdio Module InitializationEmac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptMdio Module Interrupt Events and Requests Emulation Considerations Power ManagementUser Access Completion Interrupt Link Change InterruptEmulation Control Soft FreeRpcfg Registers Ewintctl RegistersRpic Registers Mdiouser Mdiolint Stat HostCntcfg Rpcfg Register Field DescriptionsTimecfg Bit FieldRpstat Registers Rpstat Register Field DescriptionsTpic Registers Tpcfg RegistersTpcfg Register Field Descriptions Tpstat Register Field Descriptions Prescalar Configuration Register PscfgTpstat Registers PrescalecfgIntroduction Management Data Input/Output Mdio RegistersAcronym Register Description Modid Revmaj Revmin Mdio Version Register VersionMdio Version Register Version Field Descriptions Bit Field Value DescriptionMdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field DescriptionsPHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Reserved Linkint Masked Userintraw Userint Maskset Mdio User Command Complete Interrupt Mask Clear Register MaskclearMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Rxsofoverruns FRAME1024TUPNetoctets RxmofoverrunsRtlver Txmajorver Txminorver Transmit Identification and Version Register TxidverTxident RtlverTransmit Control Register Txcontrol Transmit Control Register Txcontrol Field DescriptionsTxen Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsReceive Identification and Version Register Rxidver RxidentRtlver Rxmajorver Rxminorver Receive Control Register Rxcontrol Receive Control Register Rxcontrol Field DescriptionsRxen Rxtd Nrdy Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions RxtdnchTransmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsMAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register MaceoivectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw Host Stat PendMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedHostmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchRxbroaden RxbroadchRxmulten Rxmultch Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field DescriptionsReceive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register RxbufferoffsetRxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsTxptype RxfifoflowenCmdidle GIGTxerrcode MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions TxerrchRgmiigig RxerrcodeRxerrch RgmiifullduplexSoft Free Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions SoftRxfifoflowthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions TxcellthreshTxcelldepth Rxcelldepth Addresstype Maccfig MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions TxcelldepthSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MACSRCADDR0 MACSRCADDR1MACSRCADDR0 MAC Source Address High Bytes Register Macsrcaddrhi MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5MACSRCADDR2 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field DescriptionsBit Field Value Description 31-0 MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsRndnum Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions CollcountTransmit Pacing Algorithm Test Register Tpacetest PacevalReceive Pause Timer Register Rxpause Receive Pause Timer Register Rxpause Field DescriptionsPausetimer Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions ValidMAC Address High Bytes Register Macaddrhi MACADDR2 MACADDR3 MACADDR4 MACADDR5MACADDR2 MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTXnHDP RXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TXnCPReceive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RXnCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersStatistics Register Field Descriptions Broadcast Receive Frames Register RxbcastframesMulticast Receive Frames Register Rxmcastframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesReceive Undersized Frames Register Rxundersized Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Frame Fragments Register RxfragmentsReceive Octet Frames Register Rxoctets Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Good Transmit Frames Register TxgoodframesPause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register TxdeferredTransmit Underrun Error Register Txunderrun Transmit Multiple Collision Frames Register TxmulticollTransmit Late Collision Frames Register Txlatecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Products Applications DSPRfid