Texas Instruments TMS320TCI6486 manual Purpose of the Peripheral, Features

User's Guide

SPRUEF8F – March 2006 – Revised November 2010

C6472/TCI6486 EMAC/MDIO

1Introduction

This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descriptions for each module.

The EMAC controls the flow of packet data from the processor to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the DSP through EMIC modules and CPPI buffer managers that allow efficient data transmission and reception. These two modules are considered integral to the EMAC/MDIO peripheral.

1.1Purpose of the Peripheral

The EMAC module is used on TMS320TCI6486/TMS320C6472 devices to move data between the device and another host connected to the same network, in compliance with the Ethernet protocol.

1.2Features

Two EMAC modules are integrated with the TCI6486/C6472 device. The basic feature set of the integrated EMAC modules is:

•Synchronous 10/100/1000-Mbps operation.

•Full duplex Gigabit operation (half duplex gigabit is not supported).

•Little endian and big endian support.

•Both EMAC modules support three types of interfaces to the physical layer device (PHY): reduced pin-count media independent interface (RMII), reduced pin-count gigabit media independent interface (RGMII), and source synchronous serial independent interface (S3MII).

•In addition to above four EMAC0 natively supports an additional two interfaces: standard media independent interface (MII) and standard gigabit media independent interface (GMII).

•EMAC acts as DMA master to either internal or external device memory space.

•Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support.

•Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support.

•Ether-stats and 802.3-stats statistics gathering.

•Transmit CRC generation selectable on a per-channel basis.

•Broadcast frames selection for reception on a single channel.

•Multicast frames selection for reception on a single channel.

•Promiscuous receive mode frames selection for reception on a single channel (all frames, all good frames, short frames, error frames).

•Hardware flow control.

•CPPI 3.0 compliant.

•TI adaptive performance optimization for improved half duplex performance.

•Ethernet Multicore Interrupt Combiner (EMIC) for EMAC and MDIO interrupts.

•Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, thus, allowing more work to be performed in a single call to the interrupt service routine.

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	11
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