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Texas Instruments TMS320TCI6486 manual Transmit Channel 0-7 Completion Pointer Register TXnCP

Models: TMS320TCI6486

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5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 90 and described in Table 84.

	Figure 90. Transmit Channel n Completion Pointer Register (TXnCP)
31	16

	TXnCP

	R/W-x
15	0

TXnCP

R/W-x

LEGEND: R/W = Read/Write; -n= value after reset

Table 84. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions

Bit	Field	Value	Description

31-0	TXnCP		Transmit channel n completion pointer register is written by the host with the buffer descriptor
			address for the last buffer processed by the host during interrupt processing. The EMAC uses the
			value written to determine if the interrupt should be de-asserted.

146	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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Texas Instruments TMS320TCI6486 manual Transmit Channel 0-7 Completion Pointer Register TXnCP

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramEMAC1EN Pin Description Serial Management Interface PinsSignal Description Value DescriptionIndustry Standards Compliance Statement MII Clocking Emac Clock SpecificationsClock Control Rmii ClockingRgmii Clocking Memory MapGmii Clocking 5 S3MII ClockingSystem-Level Connections EMAC0 Interface Selection PinsEMAC1 Interface Selection Pins MACSEL020, MACSEL110, and EMAC1EN DecodingMedia Independent Interface MII Connections S3MII Rgmii RmiiEmac and Mdio Signals for MII Interface Signal Name DescriptionRmtxen Emac and Mdio Signals for Rmii InterfaceReduced Media Independent Interface Rmii Connections RmcrsdvGigabit Media Independent Interface Gmii Connections RmrxerEmac and Mdio Signals for Gmii Interface GmtclkRgtxctl Emac and Mdio Signals for Rgmii InterfaceRgtxc RgrefclkRgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes DescriptionMultiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor QueuesTransmit and Receive Emac Interrupts SOP EOP Owner EOQ Tdown Pass Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format Cmplt CRCBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd-of-Queue EOQ Flag End-of-Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure FormatNext Descriptor Pointer Fragment Flag Jabber FlagOversize Flag Undersized FlagCommunications Port Programming Interface Cppi Ethernet Multicore Interrupt Combiner Emic ModuleEmic Block Diagram Pacing Block EvtoutTimed Delay State Machine Tdsm Tdsm State Transition DiagramDSM State Transition Diagram Divide-by-N State Machine DSMTransmit Pacer and Interrupt Combiner Tpic Transmit Pacer and Interrupt CombinerReceive Pacer and Interrupt Combiner Rpic Receive Pacer and Interrupt CombinerMdio Module Components Management Data Input/Output Mdio ModuleCommon Interrupt Combiner CIC Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadrEmac Module Emac Module ComponentsEmac Module Operational Overview Receive Control Media Independent InterfacesData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow ControlCRC Insertion Data TransmissionTransmit Control Adaptive Performance Optimization APOBack Off Transmit Flow ControlSpeed, Duplex, and Pause Frame Support Receive DMA Host ConfigurationPacket Receive Operation Receive Channel EnablingHardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Receive Frame ClassificationReceive Frame Treatment Summary Promiscuous Receive ModeRxmbpenable Bits Frame TreatmentReceive Overrun Transmit DMA Host ConfigurationPacket Transmit Operation Middle-of-Frame Overrun TreatmentTransmit Channel Teardown Receive and Transmit LatencyTransfer Node Priority Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Rgmii TransmissionEmic Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Mdio Module InitializationEmac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion InterruptsMdio Module Interrupt Events and Requests Host Error InterruptStatistics Interrupt Emulation Considerations Power ManagementUser Access Completion Interrupt Link Change InterruptEmulation Control Soft FreeRpcfg Registers Ewintctl RegistersRpic Registers Mdiouser Mdiolint Stat HostCntcfg Rpcfg Register Field DescriptionsTimecfg Bit FieldRpstat Registers Rpstat Register Field DescriptionsTpcfg Register Field Descriptions Tpic RegistersTpcfg Registers Tpstat Register Field Descriptions Prescalar Configuration Register PscfgTpstat Registers PrescalecfgAcronym Register Description IntroductionManagement Data Input/Output Mdio Registers Modid Revmaj Revmin Mdio Version Register VersionMdio Version Register Version Field Descriptions Bit Field Value DescriptionMdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field DescriptionsPHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Reserved Linkint Masked Userintraw Userint Maskset Mdio User Command Complete Interrupt Mask Clear Register MaskclearMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Rxsofoverruns FRAME1024TUPNetoctets RxmofoverrunsRtlver Txmajorver Txminorver Transmit Identification and Version Register TxidverTxident RtlverTxen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsRtlver Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtd Nrdy Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions RxtdnchTransmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsMAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register MaceoivectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw Host Stat PendMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedHostmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchRxmulten RxbroadenRxbroadch Rxmultch Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field DescriptionsReceive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register RxbufferoffsetRxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsTxptype RxfifoflowenCmdidle GIGTxerrcode MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions TxerrchRgmiigig RxerrcodeRxerrch RgmiifullduplexSoft Free Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions SoftRxfifoflowthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions TxcellthreshTxcelldepth Rxcelldepth Addresstype Maccfig MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions TxcelldepthSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 Bit Field Value Description 31-0 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsRndnum Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions CollcountTransmit Pacing Algorithm Test Register Tpacetest PacevalPausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions ValidMACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTXnHDP RXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TXnCPReceive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RXnCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersStatistics Register Field Descriptions Broadcast Receive Frames Register RxbcastframesMulticast Receive Frames Register Rxmcastframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesReceive Undersized Frames Register Rxundersized Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Frame Fragments Register RxfragmentsReceive Octet Frames Register Rxoctets Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Good Transmit Frames Register TxgoodframesPause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register TxdeferredTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Rfid Products ApplicationsDSP

5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

Figure 90. Transmit Channel n Completion Pointer Register (TXnCP)

Bit

Field

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