Ewintctl Registers | Texas Instruments TMS320TCI6486 instruction

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EMIC Module Registers

3 EMIC Module Registers

3.1EW_INTCTL Registers

There are six EW_INTCTL registers (one per C64x+ megamodule). These registers, shown in Figure 23, reside in the configuration space of the respective Ethernet wrappers. This register controls generation of MACTXINT, MACRXINT, and MACINT interrupts for each core.

The interrupts are classified into 3 groups:

•Common interrupts:

–MDIO_USER

–MDIO_LINT

–STAT

–HOST

•Transmit interrupts:

–TX0 through TX7

•Receive interrupts:

–RX0 through RX7

Generation of MACINTX is conditional on the following:

•At least one of the pulse interrupts in the common group is enabled.

•At least one of the enabled pulse interrupts in the common group is asserted by EMAC or MDIO.

Generation of MACTXINTX is conditional on the following:

•At least one of the pulse interrupts in the transmit group is enabled.

•At least one of the enabled pulse interrupts in the transmit group is asserted by EMAC.

Generation of MACRXINTX is conditional on the following:

•At least one of the pulse interrupts in the receive group is enabled.

•At least one of the enabled pulse interrupts in the receive group is asserted by EMAC.

Figure 23. EW_INTCTL Register

31							24
			Reserved

			0000 0000
23	22	21	20	19	18	17	16

RX7	RX6	RX5	RX4	RX3	RX2	RX1	RX0

R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15	14	13	12		10	9	8
15	14	13	12	11	10	9	8

TX7	TX6	TX5	TX4	TX3	TX2	TX1	TX0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7		5	4	3	2	1	0

	Reserved		MDIO_USER	MDIO_LINT	STAT	HOST	Reserved
	000		R/W-0	R/W-0	R/W-0	R/W-0	0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

3.2RPIC Registers

3.2.1RPCFG Registers

There are eight RPCFG registers (RPCFG0 through RPCFG7), one per receive event. This register configuration is common to all C64x+ megamodules. The RPCFG register details are shown in Figure 24 and described in Table 17.

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	71
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Texas Instruments TMS320TCI6486 manual Ewintctl Registers, Rpic Registers, Rpcfg Registers, Mdiouser Mdiolint Stat Host

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix B Appendix a List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Value Description Serial Management Interface PinsSignal Description EMAC1EN Pin Description Industry Standards Compliance Statement Rmii Clocking Emac Clock SpecificationsClock Control MII Clocking 5 S3MII Clocking Memory MapGmii Clocking Rgmii Clocking MACSEL020, MACSEL110, and EMAC1EN Decoding EMAC0 Interface Selection PinsEMAC1 Interface Selection Pins System-Level Connections S3MII Rgmii Rmii Media Independent Interface MII Connections Signal Name Description Emac and Mdio Signals for MII Interface Rmcrsdv Emac and Mdio Signals for Rmii InterfaceReduced Media Independent Interface Rmii Connections Rmtxen Rmrxer Gigabit Media Independent Interface Gmii Connections Gmtclk Emac and Mdio Signals for Gmii Interface Rgrefclk Emac and Mdio Signals for Rgmii InterfaceRgtxc Rgtxctl Rgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame Description Multiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Transmit and Receive Descriptor Queues Typical Descriptor Linked List Transmit and Receive Emac Interrupts Cmplt CRC Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format SOP EOP Owner EOQ Tdown Pass Buffer Length Next Descriptor PointerBuffer Pointer Buffer Offset Teardown Complete Tdowncmplt Flag End-of-Packet EOP FlagOwnership Owner Flag End-of-Queue EOQ Flag Example 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor Format Next Descriptor Pointer Undersized Flag Jabber FlagOversize Flag Fragment Flag Ethernet Multicore Interrupt Combiner Emic Module Communications Port Programming Interface Cppi Emic Block Diagram Evtout Pacing Block Tdsm State Transition Diagram Timed Delay State Machine Tdsm Divide-by-N State Machine DSM DSM State Transition Diagram Transmit Pacer and Interrupt Combiner Transmit Pacer and Interrupt Combiner Tpic Receive Pacer and Interrupt Combiner Receive Pacer and Interrupt Combiner Rpic Mdio Module Components Management Data Input/Output Mdio ModuleCommon Interrupt Combiner CIC Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State Monitoring Initializing the Mdio Module Mdio Module Operational Overview Reading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access Macros Emac Module Components Emac Module Emac Module Operational Overview Receive Inter-Frame Interval Media Independent InterfacesData Reception Receive Control Ieee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Adaptive Performance Optimization APO Data TransmissionTransmit Control CRC Insertion Transmit Flow Control Back Off Receive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Speed, Duplex, and Pause Frame Support Host Free Buffer Tracking Hardware Receive QOS Support Receive Frame Classification Receive Channel Teardown Frame Treatment Promiscuous Receive ModeRxmbpenable Bits Receive Frame Treatment Summary Middle-of-Frame Overrun Treatment Transmit DMA Host ConfigurationPacket Transmit Operation Receive Overrun Transmit Channel Teardown Receive and Transmit LatencyTransfer Node Priority Rgmii Transmission Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Mdio Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Emic Module Initialization Emac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion Interrupts Mdio Module Interrupt Events and Requests Host Error InterruptStatistics Interrupt Link Change Interrupt Power ManagementUser Access Completion Interrupt Emulation Considerations Soft Free Emulation Control Mdiouser Mdiolint Stat Host Ewintctl RegistersRpic Registers Rpcfg Registers Bit Field Rpcfg Register Field DescriptionsTimecfg Cntcfg Rpstat Register Field Descriptions Rpstat Registers Tpcfg Register Field Descriptions Tpic RegistersTpcfg Registers Prescalecfg Prescalar Configuration Register PscfgTpstat Registers Tpstat Register Field Descriptions Acronym Register Description IntroductionManagement Data Input/Output Mdio Registers Bit Field Value Description Mdio Version Register VersionMdio Version Register Version Field Descriptions Modid Revmaj Revmin Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register Link Field Descriptions PHY Link Status Register Link 31-2 Reserved Linkint Masked Userintraw Userint Maskset Maskclear Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Phyadrmon Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Rxmofoverruns FRAME1024TUPNetoctets Rxsofoverruns Rtlver Transmit Identification and Version Register TxidverTxident Rtlver Txmajorver Txminorver Txen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register Txteardown Rtlver Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Rxtd Nrdy Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register Macinvector MAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register Maceoivector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Host Stat Pend MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Statmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask Hostmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen Rxcafen Rxmulten RxbroadenRxbroadch Rxmultch RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register Rxbufferoffset Rxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol GIG RxfifoflowenCmdidle Txptype Txerrch MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions Txerrcode Rgmiifullduplex RxerrcodeRxerrch Rgmiigig Soft Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Soft Free Txcellthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions Rxfifoflowthresh Txcelldepth MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Txcelldepth Rxcelldepth Addresstype Maccfig Soft Reset Register Softreset Field Descriptions Soft Reset Register Softreset MACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 Bit Field Value Description 31-0 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2 Collcount Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Rndnum Paceval Transmit Pacing Algorithm Test Register Tpacetest Pausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register Txpause Valid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Match Channel Filt MACADDR0 MACADDR1 MACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex Field Descriptions MAC Index Register Macindex TXnHDP RXnHDP Transmit Channel n Completion Pointer Register TXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel n Completion Pointer Register RXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Broadcast Receive Frames Register Rxbcastframes Network Statistics RegistersStatistics Register Field Descriptions Good Receive Frames Register Rxgoodframes Pause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Multicast Receive Frames Register Rxmcastframes Receive Frame Fragments Register Rxfragments Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register Rxundersized Good Transmit Frames Register Txgoodframes Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register Rxoctets Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register Txpauseframes Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Rfid Products ApplicationsDSP