Texas Instruments TMS320TCI6486 Power Management, Emulation Considerations, Link Change Interrupt

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2.17.2.1Link Change Interrupt

The MDIO module asserts a link change interrupt (LINKINT) if there is a change in the link state of the PHY corresponding to the address in the PHYADRMON bits in the USERPHYSELn register, and if the LINKINTENB bit is also set in USERPHYSELn. This interrupt event is also captured in the LINKINTRAW bits of the LINKINTRAW register. The LINKINTRAW bits 0 and 1 correspond to USERPHYSEL0 and USERPHYSEL1, respectively.

When the interrupt is enabled and generated, the corresponding bit is also set in the LINKINTMASKED register. The interrupt is cleared by writing back the same bit to LINKINTMASKED (write to clear).

2.17.2.2User Access Completion Interrupt

A user access completion interrupt (USERINT) is asserted when the GO bit in one of the USERACCESSn registers transitions from 1 to 0 (indicating completion of a user access) and the bit in the USERINTMASKSET register corresponding to USERACCESS0 or USERACCESS1 is set. This interrupt event is also captured in bits 0 and 1 of the USERINTRAW register. USERINTRAW bits 0 and bit 1 correspond to USERACCESS0 and USERACCESS1, respectively.

When the interrupt is enabled and generated, the corresponding USERINTMASKED bit is also set in the USERINTMASKED register. The interrupt is cleared by writing back the same bit to USERINTMASKED (write to clear).

2.17.3Proper Interrupt Processing

All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, their level remains constant. However, the CPU core requires edge-triggered interrupts. To properly convert the level-driven interrupt signal to an edge-triggered signal, the application software must use the interrupt control logic of the EMIC module.

For safe interrupt processing, the software application should disable interrupts using the EMIC module interrupt control register (EW_INTCTL) upon entry to the ISR, and re-enable them upon leaving the ISR.

2.17.4Interrupt Multiplexing

The EMIC module combines different interrupt signals from both the EMAC and MDIO modules and generates a single interrupt signal that is wired to the CPU interrupt controller.

Once this interrupt is generated, the reason for the interrupt can be read from the MACINVECTOR register located in the EMAC memory map. MACINVECTOR combines the status of the following 20 interrupt signals: TXPENDn, RXPENDn, STATPEND, HOSTPEND, LINKINT, and USERINT.

The EMAC and MDIO interrupts are combined within the EMIC module and mapped to system events 70 and 71 through the use of the enhanced interrupt selector within the C64x+ core. For more details, see the Interrupt Controller chapter in the TMS320C64x+ Megamodule Peripherals Reference Guide SPRU871 and the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612).

2.18 Power Management

The power saver module integrated in this device allows the clock for different peripherals to be shut down when that peripheral is not being used. For more information on the power conservation modes available for the EMAC/MDIO peripheral, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612).

2.19 Emulation Considerations

EMAC emulation control is implemented for compatibility with other peripherals. The SOFT and FREE bits from the EMCONTROL register allow EMAC operation to be suspended.

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	69
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