Texas Instruments TMS320TCI6486 manual Serial Management Interface Pins, EMAC1EN Pin Description

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The EMAC module provides an efficient interface between the TCI6486/C6472 core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/sec) and 100Base-TX (100 Mbits/sec) in either half- or full-duplex mode, and 1000Base-T (1000 Mbits/sec) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.

Each EMAC module has a communications port programming interface (CPPI) buffer manager to manage 8K of CPPI RAM. The EMAC uses four 32-bit words as buffer descriptors that point to different buffers in the DSP memory. The CPUs create and maintain these buffer descriptors. The EMAC reads from and writes to these buffer descriptors as it transfers data to or from the buffers.

The EMIC module associated with each EMAC takes a single set of interrupts from respective EMAC and common MDIO and creates six different sets of TX, RX, and common interrupts to six cores of the TCI6486/C6472 device. In addition, this module implements the interrupt pacing operation.

The control registers of the EMAC and MDIO modules are memory mapped into device memory space via the device configuration bus.

The MDIO module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHYs connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. A single MDIO is shared by both EMACs.

MACSEL0[2:0] and MACSEL1[1:0] are device configuration pins used to select the MII interface for EMAC0 and EMAC1, respectively.

The MDIO communicates to PHY through two signals: MDCLK (output clock) and MDIO (bi-directional data). For details of MDIO operation and signals, see Section 2.8. The device has two serial management interfaces, although only one is used based on the interface selection of EMAC0. Table 1 shows the two sets of pins associated with serial management interface. One serial management interface is for RGMII (needed at 1.8-V HSTL buffer) and the other serial management interface is for non-RGMII interfaces (needed at 3.3-V LVCMOS buffers).

	Table 1. Serial Management Interface Pins
Signal	Description
GMDCLK	MII/GMII/RMII/S3MII management clock. Available on 3.3-V LVCMOS buffers.
GMDIO	MII/GMII/RMII/S3MII management data. Available on 3.3-V LVCMOS buffers.
RGMDCLK	RGMII management clock. Available on 1.8-V HSTL buffers.
RGMDIO	RGMII management data. Available on 1.8-V HSTL buffers.

As mentioned above, the management interface selection is based on the interface selection for EMAC0. If MACSEL0 is programmed to select RGMII0, the 1.8-V serial management interface is selected (RGMDIO, RGMDCLK), otherwise, the 3.3-V (GMDIO, GMDCLK) management interface is selected. Due to this programmed selection, in some cases level shifters may have to be used for the management interface. As an example, if the RGMII0 interface is selected for EMAC0 and the S3MII1 interface is selected for EMAC1, the 1.8-V serial management interface (RGMDCLK and RGMDIO) is used. Since S3MII PHY needs the 3.3-V management interface, level shifters have to be used to level translate these HSTL pins.

Also note that EMAC1 can be enabled or disabled using the EMAC1_EN internal pulldown pin that controls the I/O signals of EMAC1. The EMAC1_EN is also latched into the bit 12 of the DEVCTL register. Table 2 describes the EMAC1_EN pin.

Table 2. EMAC1_EN Pin Description

Value Description

0EMAC1 is disabled or not used.

Pulls on EMAC1 I/O are enabled (except RGMII pins) and the corresponding I/O buffers are powered down.

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	13
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