
EMAC Port Registerswww.ti.com
Table 65. MAC Control Register (MACCONTROL) Field Descriptions (continued)
Bit | Field | Value | Description |
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12 | RXFIFOFLOWEN |
| Receive FIFO flow control enable |
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| 0 | Receive flow control disabled. For |
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| 1 | Receive flow control enabled. For |
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| receive FIFO flow control is triggered. |
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11 | CMDIDLE |
| Command Idle bit |
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| 0 | Idle not commanded |
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| 1 | Idle commanded (read IDLE in the MACSTATUS register) |
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10 | Reserved | 0 | Reserved |
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9 | TXPTYPE |
| Transmit queue priority type |
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| 0 | The queue uses a |
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| 1 | The queue uses a |
|
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| for transmission |
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|
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8 | Reserved | 0 | Reserved |
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|
|
|
7 | GIG |
| Gigabit mode |
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| 0 | Gigabit mode is disabled; 10/100 mode is in operation |
|
| 1 | Gigabit mode is enabled |
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6 | TXPACE |
| Transmit pacing enable bit |
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| 0 | Transmit pacing is disabled |
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| 1 | Transmit pacing is enabled |
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5 | GMIIEN |
| GMII enable bit |
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| 0 | GMII RX and TX are held in reset |
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| 1 | GMII RX and TX are enabled for receive and transmit |
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4 | TXFLOWEN |
| Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon |
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| in |
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| regardless of this bit setting. The RXMBPENABLE bits determine whether or not received |
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| pause frames are transferred to memory. |
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| 0 | Transmit flow control is disabled. |
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| upon. |
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| 1 | Transmit flow control is enabled. |
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3 | RXBUFFERFLOWEN |
| Receive buffer flow control enable bit |
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| 0 | Receive flow control is disabled. |
|
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| sent. |
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| 1 | Receive flow control is enabled. |
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| flow control is triggered. |
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| control is triggered. |
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2 | Reserved | 0 | Reserved |
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1 | LOOPBACK |
| Loopback mode. The loopback mode forces internal |
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| FULLDUPLEX bit. The loopback bit should be changed only when the GMIIEN bit is |
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| |
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| 0 | Loopback mode is disabled |
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| 1 | Loopback mode is enabled |
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0 | FULLDUPLEX |
| Full duplex mode. The gigabit mode forces full duplex mode regardless of whether the |
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| FULLDUPLEX bit is set or not. |
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| 0 | |
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| 1 | |
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126 | C6472/TCI6486 EMAC/MDIO | SPRUEF8F |
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