Texas Instruments TMS320TCI6486 Timed Delay State Machine Tdsm, Tdsm State Transition Diagram

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2.7.2Timed Delay State Machine (TDSM)

The timed-delay state machine fully implements the functionality of the time-delay based interrupt pacing. The TIME_CFG bit field of the TPCFG and RPCFG registers (described in Section 3) is set to 0 on reset and disables this state machine. When the TIME_CFG is set to a non-zero value, an output pulse is generated after the TIME_CFG number of prescalar output periods. The counter starts counting on the first event.

The state machine has three states, WAITING, DELAY, and OUTPUT. Upon reset, the state machine is placed in the WAITING state. The state machine makes transitions between the states as shown in Figure 16. Note that states that are grayed out are transitional states, in the sense that the SM does not stay in the grayed state. While in the transitional state, it typically does an operation, like incrementing the TIME or resetting the TIME. It then changes the state to the state illustrated by the dotted line.

Figure 16. TDSM State Transition Diagram

EVT_PULSE￿=￿0￿(or)

EVT_PULSE￿=￿1￿&& TIME￿>= TIME_CFG

Waiting

				EVT		&&	PULSE=1&&￿
Time=0				_
				DIV	PULSE=0
				_
					NEXT=1		EVT
PS_TICK=0￿&&
	DIV_NEXT=0
			￿&&			Delay
_TICK=1
				_CFG
PS
	￿>=	TIME
TIME
Time=0					Time=0

CFG	￿&&
￿TIME<TIME
	Time=0
	_PULSE=1
	_NEXT=1
	EVT
	DIV

Increment

time

PS_TICK=1￿&&

TIME￿< TIME_CFG

&&￿DIV_NEXT=0

Output

EVT_PULSE=1 && TIME < TIME_CFG

Time=0

EVT_PULSE=0￿(or)

EVT_PULSE=1￿&& TIME￿>= TIME_CFG

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	43
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