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5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 56 and described in Table 50.
Figure 56. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
31 |
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| 16 |
| Reserved |
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15 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved
RX7 | RX6 | RX5 | RX4 | RX3 | RX2 | RX1 | RX0 |
PEND | PEND | PEND | PEND | PEND | PEND | PEND | PEND |
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LEGEND: R = Read only;
Table 50. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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7 | RX7PEND |
| RX7PEND masked interrupt read |
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6 | RX6PEND |
| RX6PEND masked interrupt read |
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5 | RX5PEND |
| RX5PEND masked interrupt read |
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4 | RX4PEND |
| RX4PEND masked interrupt read |
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3 | RX3PEND |
| RX3PEND masked interrupt read |
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2 | RX2PEND |
| RX2PEND masked interrupt read |
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1 | RX1PEND |
| RX1PEND masked interrupt read |
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0 | RX0PEND |
| RX0PEND masked interrupt read |
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108 | C6472/TCI6486 EMAC/MDIO | SPRUEF8F |
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