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4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 37 and described in Table 30.
Figure 37. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
31 |
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| 16 |
Reserved |
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15 | 2 | 1 | 0 |
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Reserved |
| USERINT | |
| MASKSET | ||
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LEGEND: R = Read only; R/WC = Read/Write 1 to clear;
Table 30. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field
Descriptions
Bit | Field | Value | Description |
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| Reserved | 0 | Reserved |
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USERINTMASKSET |
| MDIO user interrupt mask set for USERINTMASKED[1:0] respectively. Setting a bit to 1 will | |
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| enable MDIO user command complete interrupts for that particular USERACCESS register. |
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| MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit |
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| is 0. Writing a 0 to this register has no effect. |
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SPRUEF8F | C6472/TCI6486 EMAC/MDIO | 85 |
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