Texas Instruments TMS320TCI6486 manual 156

EMAC Port Registers www.ti.com

5.50.34 Receive FIFO or DMA Start-of-Frame Overruns Register (RXSOFOVERRUNS)

The total number of frames received on the EMAC that had either a FIFO or DMA start-of-frame (SOF) overrun. An SOF overrun frame is defined as having all of the following:

•Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

•Was of any size (including less than 64-byte and greater than RXMAXLEN-byte frames)

•The EMAC was unable to receive it because it did not have the resources to receive it (cell FIFO full or no DMA buffer available at the start of the frame).

CRC errors, alignment errors, and code errors have no effect on this statistic.

5.50.35 Receive FIFO or DMA Middle-of-Frame Overruns Register (RXMOFOVERRUNS)

The total number of frames received on the EMAC that had either a FIFO or DMA middle-of-frame (MOF) overrun. An MOF overrun frame is defined as having all of the following:

•Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

•Was of any size (including less than 64-byte and greater than RXMAXLEN-byte frames)

•The EMAC was unable to receive it because it did not have the resources to receive it (cell FIFO full or no DMA buffer available after the frame was successfully started, no SOF overrun)

CRC errors, alignment errors, and code errors have no effect on this statistic.

5.50.36 Receive DMA Start-of-Frame and Middle-of-Frame Overruns Register (RXDMAOVERRUNS)

The total number of frames received on the EMAC that had either a DMA start-of-frame (SOF) overrun or a DMA middle-of-frame (MOF) overrun. A receive DMA overrun frame is defined as having all of the following:

•Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

•Was of any size (including less than 64-byte and greater than RXMAXLEN-byte frames)

•The EMAC was unable to receive it because it did not have the DMA buffer resources to receive it (zero head descriptor pointer at the start or during the middle of the frame reception).

CRC errors, alignment errors, and code errors have no effect on this statistic.

156	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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