www.ti.com

EMAC Port Registers

5.11 MAC Input Vector Register (MACINVECTOR)

The MAC input vector register (MACINVECTOR) is shown in Figure 53 and described in Table 47.

Figure 53. MAC Input Vector Register (MACINVECTOR)

31

30

29

 

 

18

17

16

USER

LINK

Reserved

 

HOST

STAT

INT

INT

 

PEND

PEND

 

 

 

 

 

 

 

 

 

 

 

R-0

R-0

 

R-0

 

R-0

R-0

15

 

8

7

 

 

0

 

 

 

 

 

 

 

 

 

 

RXPEND

 

 

TXPEND

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

R-0

 

 

LEGEND: R = Read only; -n= value after reset

Table 47. MAC Input Vector Register (MACINVECTOR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31

USERINT

 

MDIO module user interrupt (USERINT) pending status bit

 

 

 

 

30

LINKINT

 

MDIO module link change interrupt (LINKINT) pending status bit

 

 

 

 

29-18

Reserved

0

Reserved

 

 

 

 

17

HOSTPEND

 

EMAC module host error interrupt (HOSTPEND) pending status bit

 

 

 

 

16

STATPEND

 

EMAC module statistics interrupt (STATPEND) pending status bit

 

 

 

 

15-8

RXPEND

 

Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 8 is receive channel 0.

 

 

 

 

7-0

TXPEND

 

Transmit channels 0-7 interrupt (TXnPEND) pending status bit. Bit 0 is transmit channel 0.

 

 

 

 

SPRUEF8F –March 2006 –Revised November 2010

C6472/TCI6486 EMAC/MDIO

105

Submit Documentation Feedback

 

 

Copyright © 2006–2010, Texas Instruments Incorporated

Page 105
Image 105
Texas Instruments TMS320TCI6486 manual MAC Input Vector Register Macinvector