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Freescale Semiconductor MPC8260 Manual
1360 pages 9.52 Mb
Document Number: MPC8260RM Rev. 2, 12/2005 2 How to Reach Us:79 About This Book91 Part I Overview95 Chapter 1 Overview119 Chapter 2 G2 Core147 Chapter 3 Memory MapTable3-1. Internal Memory Map 171 Part II Configuration and Reset173 Chapter 4 System Interface Unit (SIU)223 Chapter 5 Reset237 Part III The Hardware Interface241 Chapter 6 External Signals257 Chapter 7 60x Signals258 7.1 Signal ConfigurationFigure shows the grouping of the PowerQUICC IIs 60x bus signal configuration. Figure 7-1. Signal Groupings 7.2 Signal Descriptions 275 Chapter 8 The 60x Bus307 Chapter 9 PCI Bridge407 Chapter 10 Clocks and Power Control419 Chapter 11 Memory Controller420 Figure 11-1. Dual-Bus Architecture421 11.1 Features422 11.2 Basic Architecture430 11.3 Register DescriptionsTable11-2. BADDR Connections Table11-3. 60x B us Memory Controller Registers 431 11.3.1 Base Registers (BRFigure 11-6. Base Registers (BR Table11-4 describes BRx fields. 433 11.3.2 Option Registers (OR438 11.3.3 60x SDRAM Mode Register (PSDMR)Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR) Table11-8 describes PSDMR fields. LSMDR fields a re described in Table 11-9.. 441 11.3.4 Local Bus SDRAM Mode Register (LSDMR)Table11-9. LSDMR Field Descriptions Table11-8. PSDMR Field Descriptions (continued) 444 11.3.5 Machine A/B/C Mode Registers (MMR) 446 11.3.6 Memory Data Register (MDR)Table11-10. Machine x Mode Registers (M MR) (continued) Table11-11 describes MDR fields. 447 11.3.7 Memory Address Register (MAR)Figure 11-13. Memory Address Register (MAR) Table11-12 describes MAR fields. The memory address register (MAR) is shown in Figure 11-13.Figure 11-12. Memory Data Register (MDR) Table11-11. MDR Field Descriptions 448 11.3.8 60x Bus-Assigned UPM Refres h Timer (PURT)The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure11-14. Table11-14 describes LURT fields. Table11-13 describes PURT fields. 11.3.9 Local Bus-Assigned UPM Re fresh Timer (LURT)The local bus assigned UPM refresh timer register (LURT) is shown in Figure11-15. Table11-12. MAR Field Description Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT) 449 11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)The 60x bus assigned SDRAM refresh timer register (PSRT) is shown in Figure 11-16. The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure11-17. Table11-15 describes PSRT fields. 11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)Table11-14. Local Bus-Assigned UPM Refresh Timer (LURT) Table11-16 describes LSRT fields. 450 11.3.12 Memory Refresh Timer Pres caler Register (MPTPR)bus Table11-17 describes MPTPR fields. Figure 11-18 shows the memory refresh timer prescaler register (MPTPR). Figure 11-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT) Table11-16. LSRT Field Descr iptions Figure 11-18. Memory Refresh Timer Prescaler Register (MPTPR) Table11-17. MPTPR F ield Descriptions 11.3.13 60x Bus Error Status and Control R egisters (TESCR 11.3.14 Local Bus Error Status and Con trol Registers (L_TESCR 451 11.4 SDRAM Machine452 Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)453 11.4.1 Supported SDRAM Configurations11.4.2 SDRAM Power-On Initialization 11.4.3 JEDEC-Standard SDRAM Interface Commands 454 11.4.4 Page-Mode Support and Pipeline AccessesTable11-19. SDRAM Interface Commands 455 11.4.5 Bank Interleaving 11.4.5.1 Using BNKSEL Signals in Single-PowerQUICCII Bus Mode 11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA) 456 11.4.6 SDRAM Device-Specific Parameters461 11.4.7 SDRAM Interface TimingFigure 11-28 through Figure11-36 show SDRAM timing for various types of acce sses.11-44 Freescale Semiconductor 462 Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3 Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3Freescale Semiconductor 11-45 463 Figure 11-32. SDRAM Single-Beat Write, Page HitFigure 11-33. SDRAM Three-Beat Burst Write, Page Closed Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 464 11.4.8 SDRAM Read/Write Transactions465 11.4.9 SDRAM MODE-SET Command Timing11.4.10 SDRAM Refresh 466 11.4.11 SDRAM Refresh Timing11.4.12 SDRAM Configuration Examples 468 11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)469 11.5 General-Purpose Chip-Select Machine (GPCM)481 11.6 User-Programmable Machines (UPMs)499 11.7 Memory System Interface Example Using UPM519 11.8 Handling Devices with Slow or Variable Access Times 11.8.1 Hierarchica l Bus Interface Example 11.8.2 Slow Devices Example 11.9 External Master Support (60x-Compatible Mode) 525 Chapter 12 Secondary (L2) Cache Support533 Chapter 13 IEEE 1149.1 Test Access Port541 Part IV Communications Processor Module549 Chapter 14 Communications Processor Module Overview611 Chapter 16 CPM Multiplexing631 Chapter 17 Baud-Rate Generators (BRGs)637 Chapter 18 Timers645 Chapter 19 SDMA Channels and IDMA Emulation679 Chapter 20 Serial Communications Controllers (SCCs)705 Chapter 21 SCC UART Mode729 Chapter 22 SCC HDLC Mode751 Chapter 23 SCC BISYNC Mode771 Chapter 24 SCC Transparent Mode785 Chapter 25 SCC Ethernet Mode809 Chapter 26 SCC AppleTalk Mode813 Chapter 27 Serial Management Controllers (SMCs)849 Chapter 28 Multi-Channel Controllers (MCCs)899 Chapter 29 Fast Communications Controllers (FCCs)921 Chapter 30 ATM Controller and AAL0, AAL1, and AAL51017 Chapter 31 ATM AAL1 Circuit Emulation Service1063 Chapter 32 ATM AAL21065 X
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