Freescale Semiconductor MPC8260 10.5 Clock Dividers, 10.6 PowerQUICC II Internal Clock Signals

Clocks and Power Control
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 10-5
NOTE
If a clock buffer is used in the feedback path from DLLOUT to CLKIN2,
designers should ensure that the clock buffer does not include an internal
PLL as this may cause an unacceptable jitter on the clock signals.
10.4.3.2.1 CPM CLOCK and PCI Frequency Equations
The relation between CPM CLOCK frequency and PCI frequency is as follows.
If the PowerQUICC II is configured as a PCI agent device, and PCIDF = 9:
CPM/PCI = (PCIDF + 1) / 2
Otherwise:
CPM/PCI = (PCI_MODCK + 1) x (PCIDF + 1) / 2
10.5 Clock Dividers
The PLL output is twice the maximum frequency needed for all the clocks. The PLL output is sent to
general-purpose dividers (CPMDF, BUSDF), either of which can divide the double clock by a
programmable number between 1 and 16. The delay is the same for all dividers independent on the
programmable number, so the clocks are synchronized.
The output of each divider has two phases, one shifted 90° from the other. Each phase has a 50% duty
cycle.
10.6 PowerQUICC II Internal Clock Signals
The internal logic of the PowerQUICC II uses the following internal clock lines:
• CPM general system clocks (CPM_CLK, CPM_CLK_90)
• 60x bus, core bus (BUS_CLK, BUS_CLK_90)
• SCC clocks (SCC_CLK, SCC_CLK_90)
• Baud-rate generator clock (BRG_CLK)
• PCI clock (PCI_CLK) (MPC8250, MPC8265, and MPC8266 only)
The PLL synchronizes these signals to each other (but does not synchronize to BRG_CLK).
10.6.1 General System Clocks
The general system clocks (CPM_CLK, CPM_CLK_90) are the basic clocks supplied to most modules
and sub-modules on the CPM. The following points should be kept in mind:
• BUS_CLK and BUS_CLK_90 are supplied to the 60x bus and to the core.
• Many modules use both clocks (SIU, serials)
• The external clock, CLKIN, is the same as BUS_CLK