Freescale Semiconductor MPC8260 11.9.5 External Masters Timing

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-103
is sampled in the GPCM or after each READ/WRITE command in the SDRAM machine (the SDRAM
machine uses BADDR only for port sizes of 16 or 8 bits).
11.9.5 External Masters Timing
External and internal masters have similar memory access timings. However, because it takes more time
to decode the addresses of external masters, memo ry accesses by external masters start one cycle later than
those of internal masters.
As soon as the external master asserts TS, the memory controller compares the address with each of its
defined valid banks. If a match is found, the memory controller asserts the address latch enable (ALE) and
control signals to the memory devices. The memory controller asserts PSDVAL for each data beat to
indicate data beat termination on write transactions and data valid on read transactions.
The 60x bus is pipelined. The ALE pins control the external latch that latches the address from the 60x bus
and keeps the address stable for the memory access. T he memory controller asserts ALE only on the start
of new memory controller access.
Figure 11-84 shows the pipelined bus operation in 60x-compatible mode.