Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-8 Freescale Semiconductor
register each time a bus-cycle access is requested. If a match is found together with bank match, the bus
cycle is defined as a page hit. An open page is automatically closed by the SDRAM machine if the bus
becomes idle, unless ORx[PMS] is set.
11.2.3 Error Checking and Correction (ECC )
ECC can be configured for any bank as long as it is assigned to the 60x bus and is connected to a 64-bit
port size memory. ECC is generated and checked on a 64-bit basis using DP[0–7] for the bank if
BRx[DECC] = 11. If ECC is used, single errors can be corrected and all double-bit errors can be detected.
11.2.4 Parity Generation and Checking
Parity can be configured for any bank, if it is preferred. Parity is generated and checked on a per-byte basis
using DP[0–7] or LDP[0–3] for the bank if BR[DECC] = 01 for normal parity and 10 for RMW parity.
SIUMCR[EPAR] determines the global type of parity (odd or even).
Note that RMW parity can be used only for 32- or 64-bit port size banks. Also, using RMW parity on a
32-bit port size bank requires that the bus is placed in strict 60x mode. This is done by setting BCR[ETM]
(BCR[LETM] for th e local bus). Re fer to Section 4.3.2.1, “Bus Configuration Register (BCR).”
NOTE: RMW Parity and ECC Modes and Pipelined Addresses
The following applies only to .25µm (HiP4) silicon.
Due to design constraints, using RMW parity or ECC modes and pipelined
addresses (BCR[PLDP]=0) on the SDRAM interface, requires that the
PSDMR[CL] will be set to 10, choosing CAS latency of 2. If CAS latency
of 3 is needed, use BCR[PLDP] = 1 for a pipeline depth of zero.
When the PowerQUICC II is decoding a 60x read transaction into one of its internal memory-mapped
registers or dual-port RAM that was originated by an external 60x master, it will generate parity bits along
with the data bytes on DP[0–7]. The type of parity (odd or even) is determined by the SIUMCR[EPAR]
programming.
11.2.5 Transfer Error Acknowledge (TEA) Generation
The memory controller asserts the transfer error acknowledge signal (TEA) in the following cases:
• An unaligned or burst access is attempted to internal PowerQUICC II space (registers or dual-port
RAM). Note that the dual-port RAM cannot be accessed via bursts.
• The core or an external master attempts a burst a ccess to the local bus address space
• A bus monitor timeout
11.2.6 Machine Check Interrupt (MCP) Generati on
The memory controller asserts machine check interrupt (MCP) in the following cases:
• A parity error