Freescale Semiconductor MPC8260 - page 248

External Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
6-8 Freescale Semiconductor
CS[11]
AP[0]
Chip select—Output that enable specific memory devices or peripherals connected to
PowerQUICC II buses.
Address parity 0—(Input/output) The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 0 pin should give odd parity (odd
number of ‘1’s) on the group of signals that includes address parity 0 and A[0–7].
BADDR[27–28] Burst address 27–28—There are five burst address output pins. These pins are outputs of the
60x memory controller. Used in external master configuration and connected directly to the
memory devices controlled by PowerQUICC II’s memory controller. For information on the use of
these signals, see Section11.2.14, “BADDR[27:31] Signal Connections.”
ALE Address latch enable—This output pin controls the external address latch that should be used in
external master 60x bus configuration.
BCTL0 Buffer control 0—Output whose function is controlling buffers on the 60x data bus. Usually used
with BCTL1 that is multiplexed on CS10. The exact function of this pin is defined by the value of
SIUMCR[BCTLC]. See Section4.3.2.6, “SIU Module Configuration Register (SIUMCR),” for
details.
PWE[0–7]
PSDDQM[0–7]
PBS[0–7]
60x bus write enable—Outputs of the 60x bus GPCM. These pins select byte lanes for write
operations.
60x bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SDRAM devices.
60x bus UPM byte select—The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations. The timing of these pins
is programmed in the UPM. The actual driven value depends on the address and size of the
transaction and the port size of the accessed device.
PSDA10
PGPL0
60x bus SDRAM A10—(Output) from the 60x bus SDRAM controller. Part of the address when a
row address is driven and is part of the command when a column address is driven.
60x bus UPM general purpose line 0—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PSDWE
PGPL1
60x bus SDRAM write enable—(Output) from the 60x bus SDRAM controller. Should be
connected to SDRAMs’ WE input.
60x bus UPM general purpose line 1—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
POE
PSDRAS
PGPL2
60x bus output enable—The output enable pin is an output of the 60x bus GPCM. Controls the
output buffer of memory devices during read operations.
60x bus SDRAM ras—Output from the 60x bus SDRAM controller. Should be connected to
SDRAMs’ RAS input.
60x bus UPM general purpose line 2—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
Table6-1. External Signals (continued)
Signal Description