The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-12 Freescale Semiconductor
• For reads, the processor cleans or flushes during a snoop based on the
TBST input. The processor cleans for single-beat reads (TBST negated)
to emulate read-with-no-intent-to-cache operations.
• Castouts and snoop copybacks are generally marked as non-global and
are not snooped (except for reservation monitoring). However, other
masters performing DMA write operations with the same TT encoding
and marked as a global WR operation (whether global or non-global)
will cancel an active reservation during a snoop hit in the reservation
register (independent of a snoop hit in the cache).
• A non-processor read can cause the internal processor to invalidate the
corresponding cache line if it exists.
8.4.3.2 Transfer Code Signals TC[0–2]
The transfer code signals, TC[0–2], provide supplemental information about the corresponding address
(mainly regarding the source of the transaction). Note that TCx signals can be used with the TT[0–4] and
TBST to further define the current transaction.
8.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer
As shown in Table 8 -4, the transfer size signals (TSIZ[0–3]) and the transfer burst signal (TBST) together
indicate the size of the requested data transfer. These signals can be used with address bits A[27–31] and
the device port size to determine which portion of the data bus contains valid data for a write transaction
or which portion of the bus should contain valid data for a read transaction.
The PowerQUICC II uses four double-word burst transactions for transferring cache blocks. For these
transactions, TSIZ[0–3] are encoded as 0b0010, and address bits A[27–28] determine which double-word
is sent first.
Table8-3. Transfer Code Encoding for 60x Bus
TC[0–2]
60x Bus
Read Write
000 Core data trans action Any write
001 Core touch load —
010 Core instruction fetch —
011 Reserved —
100
101 Reserved
110 DMA function code 0
111 DMA function code 1