MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 28-1
Chapter 28 Multi-Channel Controllers (MCCs)
NOTE
The MPC8250 and the MPC8255 have only one MCC.
The signalling system #7 (SS7) functionality described in this chapter is not
available on rev A.1 .29µm (HiP3) silicon.
Refer to www.freescale.com for the latest RAM microcode packages that
support enhancements.
A multi-channel controller (MCC) allows the PowerQUICC II to support up to 128 separate time-division
serial channels on one peripheral. The PowerQUICC II has two MCCs. Each MCC is paired with a serial
interface (SI), allowing the MCC to communicate over any of that SI’s 4 time -division multiplexed streams
(TDM).
An MCC’s channels are assigned to a particular TDM in subgroups of 32 channels. MCC1’s channels
(0-127) may not be programmed to work with SI2, nor MCC2’s channels (128-255) to work with SI1. Each
channel of an MCC can be programmed to perform in a mode separate from the other channels of that
MCC.
Proper programming of the SI and SIRAM is responsible for the routing of timeslots within a TDM stream
to the appropriate MCC channel at the desired time. Programming the SI is covered in Chapter 15, “Serial
Interface with Time-Slot Assigner.” Users should be familiar with the information there before
proceeding.
Each MCC has the following features:
Up to 128 independent HDLC or transparent communication channels or up to 64 SS7 channels
Independent mapping for receive/transmit
Supports HDLC, transparent, or SS7 protocols on a per-channel basis
Supports additional circuit emulation service functionality when used in conjunction with ATM
AAL1
Supports interworking with AAL0
Up to 256 DMA channels with independent buffer descriptor (BD) tables
Five interrupt circular tables with programmable size and overflow identifi cation. One for transmit
and four for receive.
Global loop mode
Individual channel loop mode
Efficient bus usage (no bus usage for inactive channel or for active channels with nothing to
transmit)