Freescale Semiconductor MPC8260 11.3.4 Local Bus SDRAM Mode Register (LSDMR)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-23
11.3.4 Local Bus SDRAM Mode Register (LSDMR)
The LSDMR, shown in Figure 11-10, has the same fields as the PSDMR . Table11-9 describes LSDMR
fields.
28 EAMUX External address multiplexing enable/disable.
0 No external address multiplexing. Fastest timing.
1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE
command to the SDRAM. This is useful when external address multiplexing can cause a
delay on the address lines. Note that if this bit is set, ACTTORW should be a minimum of 2.
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the
additional delay of the multiplexing endangers the device setup time, EAMUX should be set.
Setting this bit causes the memory controller to add another cycle for each address phase.
Note that EAMUX can also be set in any case of delays on the address lines, such as address
buffers. See Section 11.4.6.7, “External Address Multiplexing Signal.”
29 BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,
instead of one. See Section11.4.6.8, “External Address and Command Buffers (BUFCMD).”
0 Normal timing for the control lines
1 All control lines except CS are asserted for two cycles
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,
as well as the address lines. If the additional delay of the buffers endangers the device setup
time, BUFCMD should be set, which causes the memory controller to add a cycle for each
SDRAM command.
30–31 CL CAS latency. Defines the timing for first read data after SDRAM samples a column address. See
Section11.4.6.3, “Column Address to First Data Out—CAS Latency.”
00 Reserved
01 1
10 2
11 3
Table11-9. LSDMR Field Descriptions
Bits Name Description
0 PBI Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction
with LSDMR[SDA10]. See Section11.4.5, “Bank Interleaving.”
0 Bank-based interleaving
1 Page-based interleaving (normal operation)
1 RFEN Refresh enable. Indicates that the SDRAM requires refresh services.
0 Refresh services are not required
1 Refresh services are required
Table11-8. PSDMR Field Descriptions (continued)
Bits Name Description