Freescale Semiconductor MPC8260 Chapter 3 Memory Map

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 3-1
Chapter 3
Memory Map
The PowerQUICC II’s internal memory resources are mapped within a contiguous block of memory. The
size of the internal space is 128 Kbytes. The location of this block within the global 4-Gbyte real memory
space can be mapped on 128 Kbytes resolution through an implementation-specific special register called
the internal memory map register (IMMR). For more information, see S e ction4.3.2.7, “Internal Memory
Map Register (IMMR).” Table 3 -1 defines the internal memory map of the PowerQUICC II.
Table3-1. Internal Memory Map
Address
(offset) Register R/W Size Reset Section/Page
CPM Dual-Port RAM
0x00000–
0x03FFF
Dual-port RAM (DPRAM1) R/W 16
Kbytes
—14.5/14-17
0x04000–
0x05FFF
Dual-port RAM (microcode only) (DPRAM)1R/W 8 Kbytes — 14.5/14-17
0x06000–
0x07FFF
Reserved — 8 Kbytes — —
0x08000–
0x08FFF
Dual-port RAM (DPRAM2) R/W 4 Kbytes — 14.5/14-17
0x09000–
0x0AFFF
Reserved — 8 Kbytes — —
0x0B000–
0x0BFFF
Dual-port RAM (DPRAM3) R/W 4 Kbytes — 14.5/14-17
0x0C000–
0x0FFFF
Reserved — 16
Kbytes
——
General SIU
0x10000 SIU module configuration register (SIUMCR) R/W 32 bits see Figure4 -28 4 .3.2.6/4-33
0x10004 System protection control register (SYPCR) R/W 32 bits 0xFFFF_FF07 4.3.2.8/4-37
0x10008 Reserved — 6 bytes — —
0x1000E Software service register (SWSR) W 16 bits undefined 4.3.2.9/4-38
0x10010–
0x10023
Reserved — 20 bytes — —
0x10024 Bus configuration register (BCR) R/W 32 bits reset
configuration
4.3.2.1/4-26
0x10028 60x bus arbiter configuration register (PPC_ACR) R/W 8 bits see Figure 4-22 4.3.2.2/4-29