Freescale Semiconductor MPC8260 19.2 SDMA Registers

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-3
Figure 19-2. SDMA Bus Arbitration (Transaction Steal)
19.2 SDMA Registers
The only user-accessible registers associated with the SDMA are the SDMA address registers, read-only
register used for diagnostics in case of an SDMA bus error, the SDMA status register and the SDMA mask
register.
19.2.1 SDMA Status Register (SDSR)
The SDMA status register (SDSR), seen in Figure 19-3, reports bus error events recognized by the SDMA
controller for all 26 SDMA channels and 4 IDMA channels. On recognition of a bus error on the local or
60x buses, the SDMA sets its corresponding SDSR bit. The SDSR is a memory-mapped register that can
be read at any time. Bits are cleared by writing ones to them; writing zeros has no effect.
Table19-1 describes SDSR fields.
0567
Field — SBER_L SBER_P
Reset 0000_0000
Addr 0x0x11018
Figure 19-3. SDMA Status Register (SDSR)
Table19 -1. SDSR Field Descriptions
Bits Name Description
0–5 — Reserved, should be cleared.
6 SBER_L SDMA channel local bus error. Indicates that the SDMA channel on the local bus had terminated
with an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no
effect. The SDMA transfer error address can be read from LDTEA, and the channel number from
LDTEM. Assertion of SBER_L causes the value inside LDTEA to stop updating. See Section 18.2.3,
“SDMA Transfer Error Address Registers (PDTEA and LDTEA).
7 SBER_P SDMA channel 60x bus error. Indicates that the SDMA channel on the 60x bus had terminated with
an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no effect.
The SDMA transfer error address is read from PDTEA. The channel number is read from PDTEM.
CLK
TS
TA
SDMA Internally
Requests the Bus
Other Transaction SDMA Transaction Other Transaction