Freescale Semiconductor MPC8260 19.5.2 Memory to/from Peripheral Transfers

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-9
19.5.1.2 Normal Mode
When external request mode is not selected (DCM[ERM] = 0), the IDMA channel operates automatically,
ignoring DREQ.
19.5.1.3 Working with a PCI Bus
NOTE
This section applies to the MPC8250, the MPC8265, and the MPC8266
only.
When working to/from the PCI bus (multiplexed with the local bus), the data usually comes on the bus in
one long burst. The alignment policy described above to support 60x/local bus bursts does not affect its
efficiency.
19.5.2 Memory to/from Peripheral Transfers
Working with peripheral devices requires the external signals DONE, DREQ, DACK to control the data
transfer using the following rules:
• The peripheral sets a request for data to be read-from/write-to by asserting DREQ as configured,
falling or rising edge sensitive.
• The peripheral transfers/samples the data when DACK is asserted.
• The peripheral asserts DONE to stop the current transfer.
• The peripheral terminates the current transfer when DONE is asserted, combined with DACK, by
the IDMA.
Peripherals are usually accessed with fixed port-size transfers. The tr ansfer sizes (STS/DTS) related to the
peripheral must be programmed to its port size; thus, every access to a peripheral yields a single bus
transaction. The maximum peripheral port size is (bus_width- 8) bytes and also should evenly divide the
buffer length, BD[Data Length].
A peripheral can also be configured to accept a burst per DRE Q assertion. In this case, the transfer size
parameter should be initialized to 32, and the accesses are made in bursts. See Table 19-8.
A peripheral can be accessed at a fixed address location or at i ncremental addresses. Setting DCM[SINC,
DINC] in the DMA channel mode register causes the address to be incremented before the next transfer;
see Section 19.8.2.1, “DMA Channel Mode (DCM).” This allows the IDMA to access a FIFO buffer the
same way it does peripherals.
DCM[S/D] determines whether the peripheral is the source or destination.
Data can be transferred between a peripheral and memory in single- or dual-address accesses:
• For dual-address accesses, the data is read from the source, temporarily stored in the IDMA
transfer buffer in the dual-port RAM, and then written to the destination.
• For single-address accesses (fly-by mode), the data is transferred directly between memory and the
peripheral. Memory responds to the address phase, while the peripheral ignores it and responds to
DACK assertions.