Freescale Semiconductor MPC8260 11.6.4 The RAM Array

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-69
Figure 11-60 shows how CSx, GPL1, and GPL2 can be controlled. A word is read from the RAM that
specifies on every clock cycle the logical bits CST1, CST2, CST3, CST4, G1T1, G1T3, G2T1, and G2T3.
These bits indicate the electrical value for the corresponding output pins at the appropriate timing.
Figure 11-60. UPM Signals Timing Example
11.6.4 The RAM Array
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 11-61. The signals
at the bottom of Figure 11-61. are UPM outputs. The selected CS is for the bank that matches the current
address. The selected BS is for the byte lanes read or written by the access.
CSx
GPL1
GPL2
CST1 CST2 CST3 CST4 CST1 CST2 CST3 CST4
G1T1 G1T3
Word 1 Word 2
CLKIN
T1
T2
T3
T4
G1T1 G1T3
G2T1 G2T3 G2T1 G2T3