MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor lix
Figures
Figure
Number Title
Page
Number
32-7 CPS Tx Queue Descriptor (TxQD).... ...................... ....................... ...................... .............. 32-14
32-8 Buffer Structure Example for CP S P ac k et s..................... ...................... .................... .. ........ 32-15
32-9 CPS TxBD.............. ...................... ...................... ....................... ...................... .................... 32- 16
32-10 CPS Packet Header Format .................... ....................... ...................... ...................... .......... 32-17
32-11 SSSAR Tx Queue Descript or............... ....................... ...................... ...................... ............ 32-17
32-12 SSSAR TxBD ............ ...................... ...................... ....................... ...................... ................ 32-19
32-13 CID Mapping Process .......... ...................... ....................... ........................ ...................... ....32- 22
32-14 AAL2 Switching .............. .. ...................... ....................... ...................... ...................... ........ 32-23
32-15 AAL2 Protocol-Specific Receive Connection Table (RCT)...............................................32-24
32-16 CPS Rx Queue Descriptor.... ...................... ....................... .. ...................... ...................... .... 32-27
32-17 CPS Receive Buffer Descriptor ..................... ....................... ...................... ...................... ..3 2 - 28
32-18 CPS Switch Rx Queue De scriptor ............. ....................... ...................... ........................ .... 32-30
32-19 Switch Receive/Transmit Buffer Descriptor.......................................................................32-30
32-20 SSSAR Rx Queue Descriptor .. ...................... ....................... ...................... ...................... ..32 - 32
32-21 SSSAR Receive Buffer De scriptor ................ ....................... ...................... ........................ 32- 33
32-22 UDC Header Table....... ...................... ...................... ....................... ...................... .............. 32-38
32-23 AAL2 Interrupt Queue Entry CID ≠ 0..... ....................... ...................... ...................... ........ 32-39
32-24 AAL2 Interrupt Queue E ntry CID = 0 ..................... ....................... ...................... .............. 32-39
33-1 Basic Concept of IMA ... ...................... ....................... ...................... ...................... .............. 33-5
33-2 Illustration of IMA Frames ...... ...................... ....................... ...................... ...................... ....33- 6
33-3 IMA Microcode Overview ............... ...................... ....................... ...................... .................. 33-6
33-4 IMA Frame and ICP Cell Formats..... ...................... ....................... ...................... .............. 33-10
33-5 IMA Transmit Task Interaction...........................................................................................33-12
33-6 Transmit Queue Normal Operating State ............. .. ....................... ...................... ................ 33-14
33-7 Transmit Queue Behavior: Link Clock Rate S a m e as TRL............................. ...................33-14
33-8 Transmit Queue Behavior: Link Clock Rate Sl o w er than TRL......................... .................33-15
33-9 Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case
Event Sequence ............. ...................... ....................... ...................... ...................... ........ 33-16
33-10 IMA Receive Task Interaction.............................................. .............................................. 33-17
33-11 IMA Microcode: Receive Process ...................................................................................... 33-21
33-12 IMA Root Table Data Structures .................... ....................... ...................... ...................... ..3 3-25
33-13 IMA Control (IMACNTL) ............... ...................... ....................... ...................... ................ 33-29
33-14 IMA Group Transmit Control (IGTCNTL)......................................................................... 33-31
33-15 IMA Group Transmit State (IGTSTATE)............................................................................33-32
33-16 Transmit Group Order Table Entry..................................................................................... 33-32
33-17 IMA Group Receive Control (IGRCNTL).......................................................................... 33-38
33-18 IMA Group Receive State (IGRSTATE).............................................................................33-39
33-19 IMA Receive Group Frame Size (IGRSTATE).................................................................. 33-40
33-20 Receive Group Order Table Entry....................................................................................... 33-40
33-21 IMA Link Transmit Control (ILTCNTL)............................................................................33-42
33-22 IMA Link Transmit State (ILTSTATE)...............................................................................33-43