Freescale Semiconductor MPC8260 11.2.7 Data Buffer Controls (BCTL, and LWR), 11.2.8 Atomic Bus Operation , 11.2.9 Data Pipelining

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-9
• An ECC double-bit error
• An ECC single bit error when the maximum number of ECC errors has be en reached
11.2.7 Data Buffer Controls (BCTL x and LWR)
The memory controller provides two data buffer controls for the 60x bus (BCTL0 and BCTL1) and one
for the local bus (LWR). These controls are activated when a GPCM- or UPM-controlled bank is acces sed
and can be disabled by setting ORx[BCTLD]. An access to an SDRAM-machine controlled bank does not
activate the BCTLx controls. The BCTL signals are asserted on the rising edge of CLKIN on the first cycle
of the memory controller operation. They are negated on the rising edge of CLKIN after the last assertion
of PSDVAL of the access is asserted. (See Section11.2.13, “Partial Data Valid Indication (PSDV AL).”) If
back-to-back memory controller operations are pending, BCTLx is not negated.
The BCTL signals have a programmable polarity. See Section 4.3.2.6, “SIU Module Configuration
Register (SIUMCR).”
11.2.8 Atomic Bus Operation
The PowerQUICC II supports the following kinds of atomic bus operations BRx[ATOM]:
• Read-after-write (RAWA). When a write access hits a memory bank in which ATOM= 01, the
PowerQUICC II locks the bus for the exclusive use of the acces sing master (internal or external).
While the bus is locked, no other device can be granted the bus. The lock is released when the
master that created the lock accesses the same bank with a read transaction. If the master fails to
release the lock within 256 bus clock cycles, the lock is released and a special interrupt is
generated. This feature is intended for CAM operations.
• Write-after-read (WARA). When a read access hits a memory bank in which ATOM= 10, the
PowerQUICC II locks the bus for the exclusive use of the acces sing master (internal or external).
During the lock period, no other device can be granted bus mastership. The lock is released when
the device that created the lock access the same bank with a write transaction. If the device fails to
release the lock within 256 bus clock cycles, the lock is released and a special interrupt is
generated.
NOTE
This mechanism does not replace the PowerPC reservation mechanism.
11.2.9 Data Pipelining
Multiple-PowerQUICCII systems that use data checking, such as ECC or parity, face a timing problem
when synchronous memories, such as SDRAM, are used. Because these devices can output data every
cycle and because the data checking requires additional data setup time, the timing constraints are
extremely hard to meet. In such systems, the user should set the data pipelining bit, BRx[DR]. This creates
data pipelining of one stage within the memory controller in which the data check calculations are done,
thus eliminating the additional data setup time requirement.