Freescale Semiconductor MPC8260 9.9.2 PCI Bus Arbitration

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-19
As a target that asserts SERR on an address parity, the PCI bridge completes the transaction on the PCI
bus, aborting internally if the transaction is a write to system memory. If PERR is asserted during a PCI
bridge write to PCI, the PCI bridge attempts to continue the transfer, allowing the tar get to abort/disconnect
if desired. If the PCI bridge detects a parity error on a read from PCI, the PCI bridge aborts the transaction
internally and continues the transfer on the PCI bus, allowing the target to abort/disconnect if desired.
In all cases of parity errors on the PCI bus, regardless of the parity-error-response bit, information about
the transaction is logged in the PCI error control capture register, the PCI error address capture register and
the PCI error data capture register; MCP is also asserted to the core as an option.
9.9.2 PCI Bus Arbitration
The PCI bus arbitration approach is access-based. Bus masters must arbitrate for each access performed
on the bus. PCI uses a central arbitration scheme where each master has its own unique request (REQx)
output and grant (GNTx) input signal. A simple request-grant handshake is used to gain access to the bus.
Arbitration for the bus occurs during the previous access so that no PCI bus cycles are consumed waiting
for arbitration (except when the bus is idle).
The PCI bridge provides arbitration for three external PCI bus masters (besides the PCI bridge itself) by
using the REQ0, REQ1, and REQ2 signals and generating the GNT0, GNT1, and GNT2 signals.
During reset, the PCI bridge samples the PCI_CFG[1] pin (and programs the PCI_ARB_DIS bit
accordingly) to determine if the arbiter is enabled or disabled. The arbiter can also be enabled or disabled
by directly programming the PCI_ARB_DIS bit in the arbiter configuration register (see
Section 9.11.2.23, “PCI Bus Arbiter Configuration Register”).
If the arbiter is disabled, the PCI bridge uses REQ0 to issue requests to an external arbiter, and uses GNT0
to receive grants from the external arbiter.
The PCI bridge implements a two-level priority, round-robin arbitration algorithm. The priority level for
the different masters can be programmed in the arbiter configuration register (see Section 9.11.2.23, “PCI
Bus Arbiter Configuration Register”).
9.9.2.1 Bus Parking
When no devices are requesting the bus, the bus is granted, or parked, for a specified device to prevent the
AD, PCI_C/BE and PAR signals from floating. The PCI bridge can be configured to either park on the PCI
bridge or park on the last master to use the bus by programming the parking-mode bit in the arbiter
configuration register (see Section 9.11.2.23, “PCI Bus Arbiter Configuration Register”).
9.9.2.2 Arbitration Algorithm
The arbitration algorithm implemented is round-robin with two priority levels. Each of the three external
PCI bus masters, plus the PCI bridge, are assigned either a high or a low priority level, as programmed in
the arbiter configuration register (see Section 9.11.2.23, “PCI Bus Arbiter Configuration Register”).
Within each priority group (high or low), the bus grant is given to the next requesting device in numerical
order, with the PCI bridge itself positioned before device 0. GNTx is asserted for devi c e x as soon as the
previously granted device begins a transaction. Conceptually, the lowest priority device at any given time