Freescale Semiconductor MPC8260 Figure 4-9 describes BCR fields.

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 4-27
Figure 4-9 describes BCR fields.
0 1 3 4 5 7 8 9 10 11 12 13 14 15
Field EBM1APD L2C L2D PLDP — DAM EAV ETM LETM EPARLEPAR
Reset — 000_0000_0000_0000
R/W R/W
16 18 19 20 21 22 25 26 27 28 31
Field NPQM — EXDD — SPAR 2ISPS1—
Reset 0000_0000_000 — 0000
R/W R/W
Addr 0x0x10024
1Depends on reset configuration sequence. See Section5.4.1, “Hard Reset Configuration Word.”
2MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Figure 4-21. Bus Configuration Register (BCR)
Table4-9. BCR Field Descriptions
Bits Name Description
0 EBM External bus mode.
0 Single PowerQUICCII bus mode is assumed
1 60x-compatible bus mode. For more information refer to Section8.2, “Bus Configuration.”
1–3 APD Address phase delay. Specifies the number of address tenure wait states for address operations
initiated by a 60x bus master. BCR[APD] specifies the number of address tenure wait states for
address operations initiated by 60x-bus devices. APD indicates how many cycles the PowerQUICCII
should wait for ARTRY
, but because it is assumed that ARTRY can be asserted (by other masters)
only on cachable address spaces, APD is considered only on transactions that hit one of the
60x-assigned memory controller banks and have the GBL signal asserted during address phase.
4 L2C Secondary cache controller. See Chapter12, “Secondary (L2) Cache Support.”
0 No secondary cache controller is assumed.
1 An external secondary cache controller is assumed.
5–7 L2D L2 cache hit delay. Controls the number of clock cycles from the assertion of TS until HIT is valid.
8 PLDP Pipeline maximum depth. See Section8.4.5, “Pipeline Control.”
0 The pipeline maximum depth is one.
1 The pipeline maximum depth is zero.
9 — Reserved, should be cleared.
10 DAM Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM). This bit is similar to
BCR[EXDD] but with opposite polarity.
0 The memory controller asserts CS on the cycle following the assertion of TS when accessing an
address space controlled by the memory controller.
1 The memory controller inserts one wait state between the assertion of TS and the assertion of CS
when accessing an address space controlled by the memory controller.