Freescale Semiconductor MPC8260 38.2 SPI Clocking and Signal Functions

Serial Periph eral Inter face (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
38-2 Freescale Semiconductor
• Works with data characters from 4 to 16 bits long
• Supports back-to-back character transmission and reception
• Master or slave SPI modes supported
• Multimaster environment support
• Continuous transfer mode for automatic scanning of a peripheral
• Supports maximum clock rates of 25 in master mode and 50 MHz in slave mode, assuming a
100-MHz system clock
• Independent programmable baud rate generator
• Programmable clock phase and polarity
• Open-drain outputs support multimaster configuration
• Local loopback capability for testing
38.2 SPI Clocking and Signal Functions
The SPI can be configured as a slave or as a master in single- or multiple-maste r environments. T he master
SPI generates the transfer clock SPICLK using the SPI baud rate generator (BRG). The SPI BRG takes its
input from BRGCLK, which is generated in the PowerQUICCII clock synthesizer.
SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and
polarity can be configured with SPMODE[CI, CP]. SPI signals can also be configured as open-drain to
support a multimaster configuration in which a shared SPI signal is driven by the PowerQUICCII or an
external SPI device.
The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave
devices. Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input
for slave devices. The dual functionality of these signals allows the SPIs in a multimaster environment to
communicate with one another using a common hardware configuration.
• When the SPI is a master, SPICLK is the clock output signal that shifts received data in from
SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to
enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI’s
SPISEL while it is master causes an error.
• When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and
transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave. In a
multimaster environment, SPISEL (always an input) is used to detect an error when more than one
master is operating.
As described in Chapter 40, “Parallel I/O Ports,” SPIMISO, SPIMOSI, SPICLK, and SPISEL are
multiplexed with port D[16–19] signals, respectively. They are configured as SPI signals through the port
D signal assignment register (PDPAR) and the port D data direction register (PDDIR), specifically by
setting PDPAR[DDn] and PDDIR[DRn].