Freescale Semiconductor MPC8260 - page 137

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-19
Figure 2-6. Data Cache Organization
Because the processor core data cache tags are single-ported, simultaneous load or store and snoop
accesses cause resource contention. Snoop accesses have the highest priority and are given first access to
the tags, unless the snoop access coincides with a tag write, in which case the snoop is r etried and must
rearbitrate for access to the cache. Loads or stores that are deferred due to snoop accesses are executed on
the clock cycle following the snoop.
Because the caches on the processor core are write-ba ck caches, the predominant type of transaction for
most applications is burst-read memory operations, followed by burst-write memory operations, and
single-beat (noncacheable or write-through) memory read and write operations. When a cache block is
filled with a burst read, the critical double word is simultaneously written to the cache and forwarded to
the requesting unit, thus minimizing stalls due to load delays.
Additionally, there can be address-only operations, variants of the burst and single-beat operations, (for
example, global memory operations that are snooped and atomic memory operations), and address retry
activity (for example, when a snooped read access hits a modified line in the cache).
Setting HID0[ABE] causes execution of the dcbf, dcbi, and dcbst instructions to be broadcast onto the
60x bus. The value of ABE does not affect dcbz instructions, which are always broadcast and snooped.
The cache operations are intended primarily for managing on-chip caches. However, the optional
broadcast feature is necessary to allow proper management of a system using an external copyback L2
cache.
The address and data buses operate independently to support pipelining and split transactions during
memory accesses. The processor core pipelines its own transactions to a depth of one level.
Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and
multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of
the internal bus without sacrificing coherency of the data. The processor core allows pending read
operations to precede previous store operations (except when a dependency exists, or in cases where a
non-cacheable access is performed), and provides support for a write operation to proceed a previously
queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data
Address Tag 1
Address Tag 2
Address Tag 3
Block 1
Block 2
Block 3
128 Sets
Address Tag 0
Block 0
8 Words/Block
State
State
State
Words 0–7
Words 0–7
Words 0–7
Words 0–7
State