G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-25

2.5.3 Exception Priorities

The exception priorities for the processor core are unchanged from those described in the G2 Core
reference Manual except for the alignment exception, whose causes are prioritized as follows:
1. Floating-point operand not word-aligned
2. lmw, stmw, lwarx, or stwcx. operand not word-aligned
3. eciwx or ecowx operand misaligned
4. A multiple or string access is attempted with MSR[LE] set
2.6 Memory Management
The following subsections describe the memory management features of the PowerPC architecture and the
PowerQUICC II implementation.

2.6.1 PowerPC MMU Model

The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for
memory accesses, and to provide access protection on blocks and pages of memory.
There are two types of accesses generated by the processor core that require address
translation—instruction accesses and data accesses to memory generated by load and store instructions.
The PowerPC MMU and exception models support demand-paged virtual memory. Virtual memory
management permits execution of programs larger than the size of physical memory; demand-paged
implies that individual pages are loaded into physical memory from system memory only when they are
first accessed by an executing program.
The PowerPC architecture supports the following three translation methods:
• Address translations disabled. Translation is enabled by setting bits in the MSR—MSR[IR] enables
instruction address translations and MSR[DR] enables data address translations. Clear ing these
bits disables translation and the effective address is used as the physical address.
• Block address translation. The PowerPC architecture defines independent four-entry BAT arrays
for instructions and data that maintain address translations for blocks of memory. Block sizes range
from 128 Kbyte to 256 Mbyte and are software selectable. The BAT arrays are maintained by
system software. The BAT registers, defined by the PowerPC architecture for block address
translations, are shown in Figure2- 2.
• Demand page mode. The page table contains a number of page table entry groups (PTEGs). A
PTEG contains eight page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes
long. PTEG addresses are entry points for table search operations.
The hashed page table is a variable-sized data structure that defines the mapping between virt ual
page numbers and physical page numbers. The page table size is a power of 2, and its starting
address is a multiple of its size.
On-chip instruction and data TLBs provide address translation in parallel with the on-chip cache
access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most
recently used page table entries. Software is responsible for maintaining the consistency of the