Freescale Semiconductor MPC8260 7.2.1 Address Bus Arbitration Sig nals

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 7-3
7.2.1 Address Bus Arbitration Sig nals
The address arbitration signals are a collection of input and output signals devices use to request address
bus mastership, recognize when the request is granted, and indicate to other devices when mastership is
granted. For a detailed description of how these signals interact, see Section 8.4.1, “Address Arbitration.”
Bus arbitration signals have no meaning in internal-only mode.
7.2.1.1 Bus Request (BR)—Output
The bus request (BR) signal is both an input and an output signal on the PowerQUICC II.
7.2.1.1.1 Address Bus Request (BR)—Output
Following are the state meaning and timing comments for the BR signal output.
State Meaning Asserted—Indicates that PowerQUICC II is requesting mastership of the address
bus. Note that BR may be asserted for one or more cycles and then deasserted due
to an internal cancellation of the bus request (for example, due to a load hit in the
touch load buffer). See Section 8.4.1, “Address Arbitration.”
Negated—Indicates that the PowerQUICC II is not requesting the address bus.
The PowerQUICC II may have no bus operation pending, it may be parked, or the
ARTRY input was asserted on the previous bus clock cycle.
Timing Comments Assertion—May occur on any cycle; does not occur if the PowerQUICC II is
parked and the address bus is idle (BG asserted and ABB input negated).
Negation—Occurs for at least one cycle following a qualified BG even if another
transaction is pending; also negated for at least one cycle following any qualified
ARTRY on the bus unless PowerQUICC II asserted ARTRY and requires a snoop
copyback; may also be negated if PowerQUICC II cancels the bus request
internally before receiving a qualified BG.
High Impedance—Occurs during a hard reset or checkstop condition
7.2.1.1.2 Address Bus Request (BR)—Input
Following are the state meaning and timing comments for the BR signal input.
State Meaning Asserted—Indicates that the external master has a bus transaction to perform and
is waiting for a qualified BG to begin the address tenure. BR may be asserted even
if the two possible pipelined address tenures have already been granted.
Negated—Indicates that the external master has no bus transaction to perform, or
if the device is parked, that it is potentially ready to start a bus transaction on the
next clock cycle (with proper qualification, see BG).
Timing Comments Assertion—May occur on any cycle; does not occur if the external master is
parked and the address bus is idle (BG asserted and ABB input negated).
Negation—Occurs for at least one cycle after a qualified BG even if another
transaction is pending; also negated for at least one cycle following any qualified
ARTRY on the bus unless this chip asserted the ARTRY and requires to perform