Freescale Semiconductor MPC8260 7.2.2 Address Transfer Start Signal

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 7-5
7.2.1.3 Address Bus Busy (ABB)
The address bus busy (ABB) signal is both an input and an output signal.
7.2.1.3.1 Address Bus Busy (ABB)—Output
Following are the state meaning and timing comments for the ABB output signal.
State Meaning Asserted—Indicates that the PowerQUICC II is the current address bus master.
The PowerQUICC II may not assume address bus ownership in case a bus request
is internally cancelled by the cycle a qualified BG would have been recognized.
Negated—Indicates that PowerQUICC II is not the current address bus master.
Timing Comments Assertion—Occurs the cycle after a qualified BG is accepted by PowerQUICC II
and remains asserted for the duration of the address tenure.
Turn-Off Sequencing—Negates for a fraction of a bus cycle (1/2 minimum,
depends on clock mode) starting the cycle following the assertion of AACK. It
then goes to the high impedance state.
7.2.1.3.2 Address Bus Busy (ABB)—Input
Following are the state meaning and timing comments for the ABB input signal.
State Meaning Asserted—Indicates that external device is the address bus master.
Negated—Indicates that the address bus may be available for use by the
PowerQUICC II (see BG). The PowerQUICC II also tracks the state of ABB on
the bus from the TS and AACK inputs. (See section on address arbitration phase.)
Timing Comments Assertion—May occur whenever the PowerQUICC II must be prevented from
using the address bus.
Negation—May occur whenever the PowerQUICC II may use the address bus.
7.2.2 Address Transfer Start Signal
In the internal only mode the address transfer start signal has no meaning.
Address transfer start signal are input and output signals that indicate that an address bus transfer has
begun.
7.2.2.1 Transfer Start (TS)
The TS signal is both an input and an output signal on the PowerQUICC II.
7.2.2.1.1 Transfer Start (TS)—Output
Following are the state meaning and timing comments for the TS output signal.
State Meaning Asserted—Indicates that the PowerQUICC II has started a bus transaction and that
the address bus and transfer attribute signals are valid. I t is also an implied data