Reference Manual (Rev 1) Errata
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor B-7
must be negated no later than 15 ns after the first rising edge of the bus clock after
CS negation for the peripheral.
19.7.2, 19-17 Add the following note:
When DREQ is level-sensitive and DONE is an input to the PowerQUICC II, the
system design must ensure that DONE is not asserted while DREQ is also
asserted. In other words, the system must not request IDMA service and
termination at the same time.
19.8.2, 19-19 In Table 19-4, the following parameters must be initialized by the user. Their
names should appear in boldface, as do other user-initialized parameters
elsewhere in the manual: IBASE, DCM, IBDPTR, DPR_BUF, SS_MAX, STS,
DTS, ISTATE.
Change the description of ISTATE in T able 19-4 to, “Internal use. Must be cleared
before every START_IDMA command.”
19.8.5, 19-25 Add the following note after the first paragraph:
The CPM always clears the valid (V) bit in an IDMA buffer descriptor before
setting the bits in IDSR that may cause an interrupt to the core.
20.3.6, 20-22 In the previous version of this document it was incorrectly stated that, in the lower
left corner of Figure20-13, “DPLL Receiver Block Diagram,” the label
“RENC πNRZI” should be replaced by “RENC = NRZI.” This is incorrect.
The correct change is as follows: it should state “RENC ≠ NRZI” and not
“RENC πNRZI.”
29.5, 29-8 Note that the previous version of this document incorrectly stated that TxBD[R]
must be set twice. Instead, it is TOD that must be set twice, as stated below:
Replace the first paragraph with the following (changes or additions appear in
boldface):
If no frame is being sent by the FCC, the CP periodically polls the R bit of the next
TxBD to see if the user has requested a new frame/buffer to be sent. Polling