Freescale Semiconductor MPC8260 - page 418

Clocks and Power Control
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
10-12 Freescale Semiconductor
The PowerQUICC II supports the two following power modes:
• Full mode—Both the chip PLL and core PLL work.
• Stop mode—Main PLL is working, core PLL is stopped, and internal clocks are disabled.
— When stop mode is entered, software sets the sleep bit in the core (HID0[10] = 1) and the clock
block freezes all clocks to the chip (the core clock and all other clocks) the main PLL remains
active.
— When stop mode is exited, the SRESET input must be asserted to the chip, the clock block
resumes clocks to all blocks and then releases the reset to the whole chip.