Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-64 Freescale Semiconductor
value driven on the external memory controller pins for a given clock cycle. Each word in the RAM arr ay
provides bits that allow a memory access to be controlled with a resolution of up to one quarter of the
external bus clock period on the byte-select and chip-select lines. Figure 11-55 shows the basic operation
of each UPM. The following events initiate a UPM cycle:
• Any internal or external device requests an external memory acces s to an address space mapped to
a chip-select serviced by the UPM
• A UPM refresh timer expires and requests a transaction, such as a DRAM refresh
• A transfer error or reset generates an exception request
Figure 11-55. User-Programmable Machine Block Diagram
The RAM array contains 64 32-bit RAM words. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-s elects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external UPMWAI T signal is sampled and synchronized by the memory
controller and the current request is frozen.
When a new access to external memory is requested by any device on the 60x or local bus, the addresses
of the transfer are compared to each one of the valid banks defined in the memory controller. When an
address match is found in one of the memory banks, BRx[MS] selects the UPM to handle this memory
access. MxMR[BSEL] assigns the UPM to the 60x or the local bus.
Note that 60x bus accesses that hit a bank allocated to the local bus are transferred to the local bus.
However, local bus accesses that hit a bank allocated to the 60x bus are ignored.
11.6.1 Requests
An internal or external device’s request for a memory access initiates one of the following patterns
(MxMR[OP] = 00):
• Read single-beat pattern (RSS)
RUN command
UPM refresh
timer request Array
Index
Generator
Internal/external
memory access request
Exception request
Index
Signals
Timing
Generator
Internal
Signals
Latch
Wait
Request
Logic
RAM Array
UPMWAIT
WAEN Bit
Internal Controls
GPL
x
, BS_
x
, CS
x
Increment
Index
(LAST = 0)Hold
(issued in software)