Freescale Semiconductor MPC8260 11.4.11 SDRAM Refresh Timing, 11.4.12 SDRAM Configuration Examples

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-48 Freescale Semiconductor
There are two levels of refresh request priority—low and high. The low priority request is generated as
soon as the refresh timer expires, this request is granted only if no other requests to the memory controller
are pending. If the request is not granted (memory controller is busy) and the refresh timer expires two
more times, the request becomes high priority and is served when the current memory controller operation
finishes.
NOTE
There are two SDRAM refresh timers, one for 60x SDRAM machines and
one for local bus SDRAM machines.
11.4.11 SDRAM Refresh Timing
The memory controller implements bank staggering for the auto refresh function. This reduces
instantaneous current consumption for memory refresh operations.
Once a refresh request is granted the memory controller begins issuing auto-refresh command to each
device associated with the refresh timer, in one clock intervals. After the last REFRESH command is issued,
the memory controller waits for the number of clocks written in the SDRAM machine’s mode register
(RFRC in P/LSDMR). The timing is shown in Figure11-39.
Figure 11-39. SDRAM Bank-Staggered CBR Refresh Timing
11.4.12 SDRAM Configuration Examples
The following sections provide SDRAM configuration examples for page- and bank-based interleaving.
CLK
CS0
SDRAS
SDCAS
MA[0–11]
WE
DQM
Data
CS1
CS2
CS3
RFRC
CBR CBR CBR CBR Activate
Z