Freescale Semiconductor MPC8260 - page 51

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xlix
Figures
Figure
Number Title
Page
Number
9-77 Inbound Message Interrupt Status Register (IMISR)............................................................ 9-81
9-78 Inbound Message Interrupt Mask Register (IMIMR)............................. ..............................9-82
9-79 Messaging Unit Contr ol Register (MUCR) ......... ......................... ...................... .................. 9-83
9-80 Queue Base Address Registe r (QBAR) ...................... ...................... .. ...................... .. .......... 9-84
9-81 DMA Controller Block Diag ra m . ...................... ....................... .. ...................... .. .................. 9-85
9-82 DMA Mode Register [0–3] (DMAMRx).............................................................................. 9-88
9-83 DMA Status Register [0–3] (DMASRx)...............................................................................9- 90
9-84 DMA Current Descriptor Address Register [0–3] (DMACDARx)...................................... 9-91
9-85 DMA Source Address Register [0–3] (DMASARx) ............................................................ 9-92
9-86 DMA Destination Address Register [0–3] (DMADARx).................................... .............. .. 9-93
9-87 DMA Byte Count Register [0–3] (DMABCRx)......................................................... ..........9-93
9-88 DMA Next Descriptor Address Register [0–3] (DMANDARx) .......................................... 9-94
9-89 DMA Chain of Segment Descri p t ors....... ....................... .. ...................... .. ...................... .. .... 9-96
10-1 System PLL Block Diagram .... .. ...................... .. ....................... ...................... .. .................... 10-2
10-2 PCI Bridge as an Age nt, Operating from the PCI System Clock ..... ...................... .............. 10-4
10-3 PCI Bridge as a Host, Generati ng the PCI System Clock... ...................... .. ...................... .. ..10- 4
10-4 PLL Filtering Circuit.............................................................................................................10-7
10-5 System Clock Cont rol Register (SCCR) .................. ......................... ...................... .............. 10-8
10-6 System Clock Mode R egister (SCMR) ....................... ........................ ...................... ............ 10-9
10-7 Relationships of SC MR Parameters..... ....................... ...................... ...................... ............ 10-10
11-1 Dual-Bus Architecture . ...................... ...................... ... ...................... ...................... .. ............ 11-2
11-2 Memory Controller Machine Selection.... ....................... ...................... ........................ ........ 11-5
11-3 Simple System Configura t i o n ........ ...................... .. ....................... .. ...................... ................ 11-6
11-4 Basic Memory Controlle r O p er ation................ ....................... ...................... .. ...................... 11-7
11-5 Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer............................11-11
11-6 Base Registers (BRx) ..... .................... .................... ..................... .................... .................... 11-13
11-7 Option Registers (ORx)—SDRAM Mode .................. ...................... ...................... .. .......... 11-15
11-8 ORx —GPCM Mod e .................... ...................... .. ....................... ...................... .. ................ 11-17
11-9 ORx—UPM Mode ..................... ...................... ....................... ........................ .................... 11-19
11-10 60x/Local SDRAM Mode Register (PSDMR/LSDMR) .................................................... 11-20
11-11 Machine x Mode Registers (Mx M R)....... .. ....................... .. ...................... .. ...................... .. 11-26
11-12 Memory Data Regist er (MDR) .................. ......................... ...................... ...................... .... 11-29
11-13 Memory Address Registe r (MAR)............. ....................... .. ...................... .. ...................... .. 11-29
11-14 60x Bus-Assigned UPM Refresh Timer (PURT)................................................................11-30
11-15 Local Bus-Assigned UPM Re f r esh Timer (LURT)..................... ...................... .. ................ 11-30
11-16 60x Bus-Assigned SDRAM Refresh Timer (PSRT)........................................................... 11-31
11-17 Local Bus-Assigned SDRAM Refresh Timer (LSRT).... ...................... ........................ ...... 11-32
11-18 Memory Refresh T im er Prescaler Register (MPTPR)................................... .....................11-32
11-19 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) ......................... 11-34
11-20 PRETOACT = 2 (2 Clock Cycles) ................... ....................... ...................... .. .................... 11-39
11-21 ACTTORW = 2 (2 Clock Cycles) ...................... .. ....................... .. ...................... .. .............. 11-40