Freescale Semiconductor MPC8260 Chapter 13 IEEE 1149.1 Test Access Port

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 13-1
Chapter 13
IEEE 1149.1 Test Access Port
The PowerQUICC II provides a dedicated user-accessible test access port (TAP) that is fully compatible
with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated
with testing high-density circuit boards have led to development of this proposed standard under the
sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The
PowerQUICC II’s implementation supports circuit-board test strategies based on this standard.
The TAP consists of five dedicated signal pins—a 16-state T AP controller and two test data registers. A
boundary scan register links all device signal pins into a single shift register. The test logic, which is
implemented using static logic design, is independent of the device system logic. The Powe rQUICCII ’s
implementation provides the capability to do the following:
• Perform boundary scan operations to check circuit-board electrical continuity.
• Bypass the PowerQUICC II for a given circuit-board test by effectively reducing the boundary
scan register to a single cell.
• Sample the PowerQUICC II system pins during operation and transparently shift out the result in
the boundary-scan register.
• Disable the output drive to pins during circuit-board testing.
NOTE
Precautions must be observed to ensure that the IEEE 1149.1-like test logic
does not interfere with nontest operation.
13.1 Overview
The PowerQUICC II’s implementation includes a T AP controlle r , a 4-bit ins truction register, and two test
registers (a 1-bit bypass register and a 475-bit boundary scan register). Figure 13-1 shows an overview of
the PowerQUICC II’s scan chain implementation.