MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor liii
Figures
Figure
Number Title
Page
Number
17-2 Baud-Rate Generator Co nfiguration Registers (BRGCx)......... ...................... .................... ..17- 2
18-1 Timer Block Diagram ........ .................... .. ..................... .. .................... .. .................... .. .......... 18-1
18-2 Timer Cascaded Mode Block Diagram .............. .. ..................... .. .................... .. .................... 18- 3
18-3 Timer Global Configuratio n Register 1 (TGCR1) .......... ...................... .................... ............ 18-4
18-4 Timer Global Configuratio n Register 2 (TGCR2) .......... ...................... .................... ............ 18-5
18-5 Timer Mode Registers (TMR1–TMR4) ............... ..................... .. ...................... .................... 18- 6
18-6 Timer Reference Registers (TRR1–T RR4 ) ................. .................... .. .................... .. .............. 18-7
18-7 Timer Capture Registers (TCR1–TC R4 ) ... ..................... .. ...................... .................... .. ........ 18-7
18-8 Timer Counter Registers (TCN1–TCN4)..............................................................................18-7
18-9 Timer Event Registers (TER1–TER 4 ) ......... ..................... .. .................... .. .................... .. ...... 18-8
19-1 SDMA Data Paths.. .................... .. .................... .. ..................... .. .................... .. ...................... 19-1
19-2 SDMA Bus Arbitration (Transaction Ste al )............. ..................... .. .................... .. ................ 19-3
19-3 SDMA Status Register (SD SR) ................. ....................... .................... ...................... .......... 19-3
19-4 SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM) ........... .. .................... .. ........ 19-4
19-5 IDMA Transfer Buffer in the Dual-Port RAM ..................... .................... .. .................... .. .... 19-7
19-6 Example IDMA Transfer Buffe r Sta tes for a Memory-to-M e m o r y Transfer
(Size = 128 Bytes).......................................................... ...... ...... ...... ...... .... ...... ...... ...... .... 19-8
19-7 Timing Requirement for DREQ Negation when IMDA Read from a Peripheral............... 19-15
19-8 IDMAx Channel’s BD Table.............. .. .................... ... .................... .. ...................... ............ 19-17
19-9 DCM Parameters.. .................... ...................... ..................... ...................... ...................... ....19-19
19-10 IDMA Event/Mask Register s (IDSR/IDMR) .... ....................... .................... ...................... 19- 24
19-11 IDMA BD Structure ................. .................... ....................... .................... ...................... ......19- 25
20-1 SCC Block Diagram....... .................... .. .................... ... ...................... .................... .. .............. 20-2
20-2 GSMR_H—General S C C Mode Register (High Order)...... .................................................20-3
20-3 GSMR_L—General SCC Mode Registe r (Low Order)........ .................... .. .................... .. .... 20-5
20-4 Data Synchronization Regis te r (DSR) . .................... ... .................... .. .................... .. .............. 20-9
20-5 Transmit-on-Demand Register (TO DR ) ....................... .................... .. ...................... .......... 20-10
20-6 SCC Buffer Descriptors (BDs). .................... .. ..................... .. .................... .. .................... .. .. 20-11
20-7 SCC BD and Buffer Memory Structure ......... .. ..................... .. .................... .. .................... .. 20 - 1 2
20-8 Function Code Registers ( RFCR and TFCR) .... ....................... .................... ...................... 20- 15
20-9 Output Delay from RTS Asserted for Synchronous Protocols........................................... 20-18
20-10 Output Delay from CTS Asserted for Synchronous Protocols........................................... 20- 18
20-11 CTS Lost in Synchronous Protocols...................................................................................20-19
20-12 Using CD to Control Synchronous Protocol Reception......................................................20-20
20-13 DPLL Receiver Block Diagram.................................................................. ........................ 20-21
20-14 DPLL Transmitter Block Diagram............................................................. ...... ...... ...... ...... .20-22
20-15 DPLL Encoding Examples ................... ....................... .................... ...................... .............. 20-23
21-1 UART Character Format .................. .................... ....................... .................... ..................... .21-1
21-2 Two UART Multidrop Configurations..................................................................................21-7
21-3 Control Character Table ................. .................... .. ....................... .................... .. .................... 21 -8
21-4 Transmit Out-of-Sequence Regis ter (TOSEQ) ................. .. .................... .. .................... .. ...... 21-9