Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-16 Freescale Semiconductor
Table11-5. OR
x
Field Descriptions (SDRAM Mode)
Bits Name Description
0–11 SDAM SDRAM address mask. Provides masking for corresponding BR
x
bits. By masking address
bits independently, SDRAM devices of different size address ranges can be used. Clearing
bits masks the corresponding address bit. Setting bits causes the corresponding address
bit to be compared with the address pins. Address mask bits can be set or cleared in any
order, allowing a resource to reside in more than one area of the address map. SDAM can
be read or written at any time.
0000_0000_0000 4Gbytes
1000_0000_0000 2 Gbytes
1100_0000_0000 1 Gbyte
1110_0000_0000 512 Mbytes
1111_0000_0000 256 Mbytes
1111_1000_0000 128 Mbytes
1111_1100_0000 64 Mbytes
1111_1110_0000 32 Mbytes
1111_1111_0000 16 Mbytes
1111_1111_1000 8 Mbytes
1111_1111_1100 4 Mbytes
1111_1111_1110 2 Mbytes
1111_1111_1111 1 Mbyte
Note:If xSDMR[PBI] = 0, the maximum size of the memory bank should not exceed 128
Mbytes.
12–16 LSDAM Lower SDRAM address mask. Clearing LSDAM implements a minimum size of 1 Mbyte.
SDRAM Page Information
17–18 BPD Banks per device. Sets the number of internal banks per SDRAM device.
00 2 internal banks per device
01 4 internal banks per device
10 8 internal banks per device (not valid for 128-Mbyte SDRAMs)
11 Reserved
Note:For 128-Mbyte SDRAMs, BPD must be 00 or 01.
19–22 ROWST Row start address bit. Sets the demultiplexed row start address bit. The value of ROWST
depends on SDMR[PBI].
For xSDMR[PBI] = 0:
0010 A7
0100 A8
0110 A9
1000 A10
1010 A11
1100 A12
1110 A13
Other values are reserved
For xSDMR[PBI] = 1:
0000 A0
0001 A1
...
1100 A12
1101–1111 Reserved
23–25 NUMR Number of row address lines. Sets the number of row address lines in the SDRAM device.
000 9 row address lines
001 10 row address lines
010 11 row address lines
011 12 row address lines
100 13 row address lines
101 14 row address lines
110 15 row address lines
111 16 row address lines