Freescale Semiconductor MPC8260 19.5.3 Controlling 60x Bus Bandwidth

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-11
related to the dual-port RAM bus are not relevant in fly-by mode. Each DREQ assertion triggers a transfer
the size of the peripheral port. All transfers are made in single memory ac cesses accompanied by DACK
assertion. When DONE is asserted externally or a STO P_IDMA command is issued, the current transfer is
stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see Section19.8.4, “IDMA
Event Register (IDSR) and Mask Register (IDMR).”
In fly-by mode, a peripheral can be configured to handle a burst per DREQ assertion if STS is programmed
to 32. The first phase of the transfer aligns the data to the burst boundary so that subsequent accesses can
be performed in bursts.
19.5.2.2.1 Peripheral-to-Memory Fly-By Transfers
During peripheral-to-memory fly-by transfers, the IDMA controller writes to memory while
simultaneously asserting DACK. The constant assertion of DACK enables the controller to write to
memory as soon as the peripheral outputs data to the bus. Thus, data is transferred from a peripheral to
memory in one data phase instead of two, increasing throughput.
For proper operation, STS must equal the peripheral port size.
19.5.2.2.2 Memory-to-Peripheral Fly-By Transfers
During memory-to-peripheral fly-by transfers, the IDMA controller reads from memory while
simultaneously asserting DACK.
The constant assertion of DACK enables the controller to read from memory as soon as the peripheral
samples the data bus. Thus, data is transferred from memory to a peripheral in one data phase instead of
two, increasing throughput.
For proper operation, DTS must equal the peripheral port size.
19.5.3 Controlling 60x Bus Bandwidth
STS, DTS, and SS_MAX can be used to control the 60x bus bandwidth occupied by the IDMA channel.
In every mode except fly-by mode, at least one transfer size parameter (STS/DTS) must be initialized to
the SS_MAX value. For memory-to-memory transfers, the other transfer size parame ter can be initia lized
to a smaller value used to control the 60x bus bandwidth. For example, if the transfer size is N*32 bytes,
each time the DMA controller wins arbitration, it transfers N bursts before releasing the bus. When
SS_MAX bytes have been transferred, the controller reverts to single transactions (double-word, word,
half-word, or byte).
Memory-to-memory transfer sizes must evenly divide into SS_MAX and also be a multiple of 32 (for
bursting); see Table19-7.
The size of the IDMA transfer buffer in the dual-port RAM should be determined by the largest transfer
(usually SS_MAX + 32 bytes) needed by one of the buses, while the other transfer size can be programmed
to control the bandwidth of the other bus.
Summarizing the above, a larger DMA transfer size provides for greater microcode efficiency and lower
DMA bus latency, because the DMA controller does not release the 60x bus until the transfer is completed.
If the DMA priority on the 60x bus is high, however, other 60x masters may experience a high bus latency.