Freescale Semiconductor MPC8260 8.3.2 Address Pipelining and Split-Bus Transactions

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-6 Freescale Semiconductor
system reset by sampling configuration pins. See Section 4.3.2.2, “60x Bus Arbiter Configuration Register
(PPC_ACR),” for more information.
The PowerQUICC II controls bus access through the bus request (BR) and bus grant (BG) signals. It
determines the state of the address and data bus busy signals by monitoring DBG, TS, AACK, and TA, and
it qualifies them with ABB and DBB.
The following signals are used for address bus arbitration:
•BR (bus request)—A device asserts BR to request address bus mastership.
•BG (bus grant)—Assertion indicates that a bus device may, with proper qualification, assume
mastership of the address bus. A qualified bus grant occurs when BG is asserted while ABB and
ARTRY are negated.
•ABB (address bus busy)—A device asserts ABB to indicate it is the cur rent address bus master.
Note that if all devices assert ABB with TS and would normally negate ABB after AACK is
asserted, the devices can ignore ABB because the PowerQUICC II can internally generate ABB.
The PowerQUICC II’s ABB, if enabled, must be tied to a pull-up resistor.
The following signals are used for data bus arbitration:
•DBG (data bus grant)—Indicates that a bus device can, with the proper qualification, assume data
bus mastership. A qualified data bus grant occurs when DBG is asserted while DBB and ARTRY
are negated.
•DBB (data bus busy)—Assertion by the device indicates that the device is the current data bus
master. The device master always assumes data bus mastership if it needs the data bus and is given
a qualified data bus grant (see DBG). Note that if all devices assert DBB in conjunction with
qualified data bus grant and would normally negate DBB after the last TA is asserted, the devices
can ignore DBB because the PowerQUICC II can generate DBB internally. The PowerQUICC II’s
DBB signal, if enabled, must be tied to a pull-up resistor.
The following is a summary of rules for arbitration:
• Preference among devices is determined at the request level. The PowerQUICCII supports eight
levels of bus requests.
• When no bus device is requesting the address bus, the PowerQUICC II parks the device selected
in the arbiter configuration register on the bus.
For more information, see Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR).”
8.3.2 Address Pipelining and Split-Bus Transactions
The 60x bus protocol provides independent address and data bus capability to support pipelined and
split-bus transaction system organizations. Address pipelining allows the next address tenure to begin
before the current data tenure has finished. Although this ability does not inherently reduce memory
latency, support for address pipelining and split-bus transactions can greatly improve effective
bus/memory throughput. These benefits are most fully realized in shared-memory, multiple-master
implementations where bus bandwidth is critical to system performance.