External Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 6-13
L_A27
PCI_GNT21
CPCI_HS_ENUM1
Local bus address 27—Local bus address bit 27 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
PCI arbiter grant 2—PCI grant 2 output pin. When the PowerQUICC II’s internal PCI arbiter is
used, assertion of PCI_GNT2 indicates that the external PCI device that requested the PCI bus
with PCI_REQ2 pin is granted the bus.
CompactPCI Hot Swap Enumerator—Hot Swap ENUM output pin. In CompactPCI system, when
the PowerQUICC II’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface
to connect to the host as the enumeration request.
L_A28
PCI_RST1
CORE_SRESET
Local bus address 28—Local bus address bit 28 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
PCI reset—PCI reset output pin. When the PowerQUICC II is the host in the PCI system,
PCI_RST is an output.
Core system reset—This is an input to the core. When this input pin is asserted the core branches
to its reset vector.
L_A29
PCI_INTA1
Local bus address 29—Local bus address bit 29 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
PCI INTA—(output) When the PowerQUICC II is an agent of the PCI system, this pin is an output
used by the PowerQUICC II to signal an interrupt to the PCI host. (When the PowerQUICC II is
the host in the PCI system, the general IRQ pins are used for delivering PCI interrupts to the host.)
L_A30
PCI_REQ21
Local bus address 30—Local bus address bit 30 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
PCI arbiter request 2—PCI request 2 input pin. When the PowerQUICC II’s internal PCI arbiter is
used, assertion of this pin indicates that an external PCI device is requesting the PCI bus.
L_A31
DLLOUT1
Local bus address 31—Local bus address bit 31 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
DLL Clock Out—DLL output pin. This is the DLL output reference clock. See Figure10-2 and
Figure10-3.
LCL_D[0–31]
PCI_AD[31-0]1
Local bus data—Local bus data input/output pins. In the local data bus bit 0 is most significant
and bit 31 is least significant.
PCI address/data—PCI bus address/data input/output pins. During an address phase
PCI_AD[31-0] contains a physical address, during a data phase PCI_AD[31-0] contains the data
bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb.
Table6-1. External Signals (continued)
Signal Description