Freescale Semiconductor MPC8260 11.6.4.4 Signals Negation, 11.6.4.5 The Wait Mechanism

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-78 Freescale Semiconductor
Figure 11-65. UPM Read Access Data Sampling
11.6.4.4 Signals Negation
When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the next cycle all the
UPM signals are negated unconditionally (driven to logic ‘1’).
This negation will not occur only if there is a back-to-back UPM request pending. In this case the sig nals
value on the cycle following the LAST bit, will be taken from the first line of the pending UPM routine.
11.6.4.5 The Wait Mechanism
The WAEN bit in the RAM array word, shown in Table11-36., can be used to enable the UPM wait
mechanism in selected UPM RAM words. Note that the WAEN bit needs to be set in two consecutive UPM
words to get the desired operation.
If the UPM reads a RAM word with the WAEN bit set, the external UPMWAIT signal is sampled by the
memory controller in the following cycle and the request is frozen. The UPMWAIT signal is sampled at
the rising edge of CLKIN. If UPMWAIT is asserted and WAEN= 1 in the previous UPM word, the UPM
is frozen until UPMWAIT is negated. The value of the external pins driven by the UPM remains as
indicated in the previous word read by the UPM. When UPMWAIT is negated, the UPM continues its
normal functions. Note that during the wait cycles, the UPM negates PSDVAL.
Figure 11-66 shows how the WAEN bit in the word read by the UPM and the UPMWAIT signal are used
to hold the UPM in a particular state until UPMWAIT is negated. As the example in Figure11-66 shows,
the CSx and GPL1 states (C12 and F) and the WAEN value (C) are frozen until UPMWAIT is recognized
as deasserted. WAEN is typically set before the line that contain UTA = 1.
To internal
data bus
CLKIN
UPMx selected to handle the transfer
AND
(GPL4xDIS = 1) and RD/WR and DLT2x
Data Bus
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