Freescale Semiconductor MPC8260 17.2 Autobaud Operation on a UART

Baud-Rate Generators (BRGs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
17-4 Freescale Semiconductor
17.2 Autobaud Operation on a UART
During the autobaud process, a UART deduces the baud rate of its received character stream by examining
the received pattern and its timing. A built-in autobaud control function automatically measures the length
of a start bit and modifies the baud rate accordingly.
If the autobaud bit BRGCx[ATB] is set, the autobaud control function starts searching for a low level on
the corresponding RXDn input, which it assumes marks the beginning of a start bit, and begins counting
the start bit length. During this time, the BRG output clock toggles for 16 BRG clock cycles at the BRG
source clock rate and then stops with BRGOn in the low state.
When RXDn goes high again, the autobaud control block rewrites BRGCx[CD, DIV16] to the divide ratio
found, which at high baud rates may not be exactly the final rate desired (for example, 56,600 may result
rather than 57,600). An interrupt can be enabled in the UART SCC event register to report that the
autobaud controller rewrote BRGCx. The interrupt handler can then adjust BRGCx[CD, DIV16] (see
Table17-3.) for accuracy before the first character is fully received, ensuring that the UART recognizes
all characters.
After a full character is received, the software can verify that the character matches a predefined value
(such as ‘a’ or ‘A’). Software should then check for other characters (such as ‘t’ or ‘T’) and program the
preferred parity mode in the UART’s protocol-specific mode register (PSMR).
Note that the SCC associated with this BRG must be programmed to UART mode and select the 16×
option for TDCR and RDCR in the general SCC mode register low. Input frequencies such as 1.8432, 3.68,
7.36, and 14.72 MHz should be used. The SCC performing the autobaud function must be connected to
that SCC’s BRG; that is, SCC2 must be clocked by BRG2, and so on.
Also, to detect an autobaud lock and generate an interrupt, the SCC must r eceive three full Rx clocks from
the BRG before the autobaud process begins. To do this, first clear BRGCx[ATB] and enable the BRG Rx
clock to the highest frequency. Then, immediately before the autobaud process starts (after device
initialization), set BRGCx[ATB].
Table17-2. BRG External Clock Source Options
BRG
CLK
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
BRG1 V V
BRG2 V V
BRG3 V V
BRG4 V V
BRG5 V V
BRG6 V V
BRG7 V V
BRG8 V V