ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
34-10 Freescale Semiconductor
34.4.1.3 TC Layer Event Register [1–8] (TCERx)

The TC layer event registers (TCERx), as shown in Figure 34-7, records error events for each TC block.

TCER event bits are cleared by writing ones to them.

The TCER bits are described in Table 34-4.

0 1 2 3 4 5 9101112131415
Field OR UR CDT MS PARE — ROF TOF EOF COF IOF FOF
Reset 0000_0000_0000_0000
R/W R/W

Figure 34-7. TC Layer Event Register (TCER

x
)

Table34-4. TCER

x

Field Descriptions

Bits Name Description
0 OR Overrun. Rx FIFO OverFlow.
Set when Rx FIFO is full and another complete cell is received. The cell is discarded.
1 UR Underrun. No ATM cell to transmit.
Set when the Tx FIFO is empty and the transmission of a cell is completed. An idle cell
is sent.
This interrupt is enabled only if TCMODE[URE] is set.
The idle cell header is: 0x00000001 (I.432), whose HEC is: 0x52
The idle cell payload is:0x6A (I.432).
2 CDT Cell delineation toggled.
Set when the cell delineation bit (CD) in TCGSR has changed.
3 MS Misplaced Txsyn signal
Set when Txsyn is out of place. (The first Txsyn is by definition always in place.)
4 PARE Parity event
Set when parity from UTOPIA to transmit is wrong.
5-9 — Reserved
10 ROF Received cell counter overflow
Set when the received cells counter passes its maximum value.
11 TOF Transmitted cell counter overflow
Set when the transmitted cells counter passes its maximum value.
12 EOF Err ored cells counte r overflow
Set when the errored cells counter passes its maximum value.
13 COF Corrected cells counter overflow
Set when the corrected cells counter passes its maximum value.
14 IOF Tx Idle cells counter overflow
Set when the Tx idle cells counter passes its maximum value.
15 FOF Filtered cells counter overflow
Set when the filtered cells counter passes its maximum value.