Freescale Semiconductor MPC8260 - page 23

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xxi
Contents
Paragraph
Number Title
Page
Number
16.4.3 CMX SI2 Clock Route Register (CMXSI2CR).......................................................16-12
16.4.4 CMX FCC Clock Rout e Reg i ster (CMXFCR) .. ...................... ...................... .......... 16-13
16.4.5 CMX SCC Clock Rout e Reg i ster (CMXSCR) .. ...................... ...................... .......... 16-16
16.4.6 CMX SMC Cloc k Route Register (CMXSM R).... ...................... ...................... ...... 16-19
Chapter 17
Baud-Rate Generators (BRGs)
17.1 BRG Configuration Registers 1–8 (BRGCx) ................................................................ 17-2
17.2 Autobaud Operation on a UART .................... ....................... ...................... .................. 17-4
17.3 UART Baud Rate Examples ... ...................... ....................... ...................... .................... 17-5
Chapter 18
Timers
18.1 Features..........................................................................................................................18-1
18.2 General-Purpose Timer Units ................... ..................... ...................... ...................... .... 18-2
18.2.1 Cascaded Mod e ................. ...................... ....................... ...................... ...................... 18 -3
18.2.2 Timer Global Confi g u r ation Registers (TGCR1 and TGC R 2 ) ................ .. ................ 18-3
18.2.3 Timer Mode Registe rs (TMR1–TMR4)........... .. ...................... ...................... ............ 18-5
18.2.4 Timer Reference Reg i s ters (TRR1–TRR4) ......... ...................... ...................... .. ........ 18-6
18.2.5 Timer Capture Regi st e r s (TCR1–TCR4) ....................... ...................... ...................... 18- 7
18.2.6 Timer Counters (TCN1–TCN4)................................................................................. 18-7
18.2.7 Timer Event Regis te rs (TER1–TER4).... ....................... ...................... ...................... 18- 7
Chapter 19
SDMA Channels and IDMA Emulation
19.1 SDMA Bus Arbitratio n and Bus Transfers .................. ........................ ...................... .... 19-2
19.2 SDMA Registers ............. .. ...................... ....................... ...................... ...................... ....19-3
19.2.1 SDMA Status R egister (SDSR) .............. ....................... ...................... ...................... 19- 3
19.2.2 SDMA Mask Register (SDMR).... ....................... ...................... ...................... .......... 19-4
19.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA).............................19-4
19.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM).........................19-4
19.3 IDMA Emulation .......... ...................... ....................... ...................... ...................... ........ 19-5
19.4 IDMA Features ....... ...................... ....................... ...................... ...................... .............. 19-5
19.5 IDMA Transfers ...................... ...................... ..................... ...................... ...................... 19-6
19.5.1 Memory-to- Me mory Transfers ................... .. ....................... ...................... ................ 19-6
19.5.1.1 External Request Mode..... ...................... ....................... ...................... .. ................ 19-8
19.5.1.2 Normal Mode...... .. ...................... ....................... ...................... ...................... ........ 19-9
19.5.1.3 Working with a PCI Bus. .. ...................... ....................... ...................... .................. 19-9