Reference Manual (Rev 1) Errata
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
B-6 Freescale Semiconductor
Also, replace the description of REV_NUM in Table 14-15 with the following
(changes or additions appear in boldface):
15.4.5, 15-15 In the first and third items under the ‘Static routing’ bullet, it should state TDM
rather than TSA.
15.5.2, 15-19 In Table 15-5, add the following to the definition of configuration 00 for
RFSDx (SIxMR[6–7]) and TFSDx (SIxMR[14–15]):
If frame sync delay is not used and if a frame sync is issued early during the last
bit of the previous frame, data corruption can occur on all subsequent frames. To
avoid this problem, program a 1-, 2-, or 3-bit sync delay.
19.7.1, 19-15 Under ‘Note,’ replace “do one of the following” with “do the following.” Then
replace the two bulleted items with the following:
First, initialize all registers, parameter RAM, and buffer descriptors ready
(TxBD[R]=1) for an IDMA. Then, write an IDMA START command to CPCR
and wait for CPCR[FLG] to be cleared. Then, wait an additional 50 CPM clocks.
At this point, it is safe to program the parallel port registers for the IDMA.
19.7.1.1, 19-16 Add the following:
When an IDMA is in external request mode and its DREQ is set to level-sensitive
mode, the IDMA requests service by the CPM whenever its DREQ signal is
active. This is true regardless of whether or not an IDMA is in progress. Therefore,
whenever the IDMA's DREQ is active, all CPM peripherals with a priority lower
than the IDMA do not receive service. The IDMA priority can be configured via
RCCR[DRxQP] and, because DREQ may be active for long periods, systems that
configure DREQ to be level-sensitive must select priority option 3 for DRxQP to
avoid starving other CPM peripherals (see Table 14-2 and Table 14-3). If more
than one IDMA is given the same priority, the lower-numbered IDMA has priority
over a higher numbered IDMA. For example, if both IDMA3 and IDMA4 are
given priority option 3, then IDMA3 will have priority over IDMA4.
In addition to the issue described in the previous paragraph, there is another issue
to consider when an IDMA is in external request mode and its DREQ is set to
level-sensitive mode. When these are true and the external peripheral device is
controlled by one of the memory controllers of PowerQUICC II, such as the UPM
or GPCM controller, DREQ must be negated before tmax to prevent DREQ
negation from triggering an extra IDMA transfer cycle. Refer to the f ollowing
figure. Note that T = 2 xCPM_CLK. In the example shown, CPM_CLK = 133
MHz, with an approximate clock cycle of 7.5 ns. Therefore, T = 15 ns and DREQ
RAM Base + 0x8AF0 REV_NUM Hword Microcode revision number. If working with newer silicon than what is
shown below, consult the product page on the web.
For .29-µm (HiP3) devices: Rev A.1—0x0001
Rev B.2—0x003B
Rev C.2—0x007B
For .25-µm (HiP4) devices: Rev A.0—0x000D
Rev B.1—0x002D
Rev C.0—0x002D